X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fcorenet_ds.h;h=8ed37a58c200458fe8c7d48bfb5048a126b69147;hb=05f132d74d173854df79bc5541699c3db144e42a;hp=adf9906bce9f3e18c8989db8267e100d9c4a7d7b;hpb=9023ae305919d0aecb4a22726b9d08c6b08189d7;p=u-boot diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index adf9906bce..8ed37a58c2 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -33,6 +33,15 @@ #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #endif +#ifdef CONFIG_SRIOBOOT_SLAVE +/* Set 1M boot space */ +#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) +#define CONFIG_SYS_SRIOBOOT_SLAVE_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIOBOOT_SLAVE_ADDR) +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc +#define CONFIG_SYS_NO_FLASH +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE #define CONFIG_E500 /* BOOKE e500 family */ @@ -56,7 +65,6 @@ #define CONFIG_PCI /* Enable PCI/PCIE */ #define CONFIG_PCIE1 /* PCIE controler 1 */ #define CONFIG_PCIE2 /* PCIE controler 2 */ -#define CONFIG_PCIE3 /* PCIE controler 3 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ @@ -69,7 +77,9 @@ #define CONFIG_ENV_OVERWRITE #ifdef CONFIG_SYS_NO_FLASH +#ifndef CONFIG_SRIOBOOT_SLAVE #define CONFIG_ENV_IS_NOWHERE +#endif #else #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI @@ -89,6 +99,7 @@ #elif defined(CONFIG_SDCARD) #define CONFIG_SYS_EXTRA_ENV_RELOC #define CONFIG_ENV_IS_IN_MMC +#define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OFFSET (512 * 1097) @@ -97,6 +108,12 @@ #define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_OFFSET (5 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIOBOOT_SLAVE) +#define CONFIG_ENV_IS_IN_REMOTE +#define CONFIG_ENV_ADDR 0xffe20000 +#define CONFIG_ENV_SIZE 0x2000 +#elif defined(CONFIG_ENV_IS_NOWHERE) +#define CONFIG_ENV_SIZE 0x2000 #else #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) @@ -144,19 +161,6 @@ #define CONFIG_SYS_L3_SIZE (1024 << 10) #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xfe000000 /* relocated CCSRBAR */ -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS 0xffe000000ull /* physical addr of CCSRBAR */ -#else -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#endif -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ - #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull @@ -182,7 +186,11 @@ #define CONFIG_DDR_SPD #define CONFIG_FSL_DDR3 +#ifdef CONFIG_P3060QDS +#define CONFIG_SYS_SPD_BUS_NUM 0 +#else #define CONFIG_SYS_SPD_BUS_NUM 1 +#endif #define SPD_EEPROM_ADDRESS1 0x51 #define SPD_EEPROM_ADDRESS2 0x52 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ @@ -212,7 +220,6 @@ (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 -#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ #ifdef CONFIG_PHYS_64BIT #define PIXIS_BASE_PHYS 0xfffdf0000ull @@ -243,8 +250,6 @@ #endif /* Nand Flash */ -#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) -#define CONFIG_NAND_FSL_ELBC #ifdef CONFIG_NAND_FSL_ELBC #define CONFIG_SYS_NAND_BASE 0xffa00000 #ifdef CONFIG_PHYS_64BIT @@ -285,11 +290,10 @@ #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ #endif -#endif /* CONFIG_NAND_FSL_ELBC */ #else #define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */ #define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */ -#endif +#endif /* CONFIG_NAND_FSL_ELBC */ #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 @@ -385,6 +389,54 @@ #endif #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ +/* + * SRIOBOOT - MASTER + */ +#ifdef CONFIG_SRIOBOOT_MASTER +/* master port for srioboot*/ +#define CONFIG_SRIOBOOT_MASTER_PORT 0 +/* #define CONFIG_SRIOBOOT_MASTER_PORT 1 */ +/* + * for slave u-boot IMAGE instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS1 0xfef080000ull +#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS1 0xfff80000ull +#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SIZE 0x80000 /* 512K */ +#define CONFIG_SRIOBOOT_SLAVE_IMAGE_LAW_PHYS2 0xfef080000ull +#define CONFIG_SRIOBOOT_SLAVE_IMAGE_SRIO_PHYS2 0x3fff80000ull +/* + * for slave UCODE instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIOBOOT_SLAVE_UCODE_LAW_PHYS 0xfef020000ull +#define CONFIG_SRIOBOOT_SLAVE_UCODE_SRIO_PHYS 0x3ffe00000ull +#define CONFIG_SRIOBOOT_SLAVE_UCODE_SIZE 0x10000 /* 64K */ +/* + * for slave ENV instored in master memory space, + * PHYS must be aligned based on the SIZE + */ +#define CONFIG_SRIOBOOT_SLAVE_ENV_LAW_PHYS 0xfef060000ull +#define CONFIG_SRIOBOOT_SLAVE_ENV_SRIO_PHYS 0x3ffe20000ull +#define CONFIG_SRIOBOOT_SLAVE_ENV_SIZE 0x20000 /* 128K */ +/* slave core release by master*/ +#define CONFIG_SRIOBOOT_SLAVE_HOLDOFF +#define CONFIG_SRIOBOOT_SLAVE_BRR_OFFSET 0xe00e4 +#define CONFIG_SRIOBOOT_SLAVE_RELEASE_MASK 0x00000001 /* release core 0 */ +#endif + +/* + * SRIOBOOT - SLAVE + */ +#ifdef CONFIG_SRIOBOOT_SLAVE +/* slave port for srioboot */ +#define CONFIG_SRIOBOOT_SLAVE_PORT0 +/* #define CONFIG_SRIOBOOT_SLAVE_PORT1 */ +#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR 0xFFE00000 +#define CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR_PHYS \ + (0x300000000ull | CONFIG_SYS_SRIOBOOT_UCODE_ENV_ADDR) +#endif + /* * eSPI - Enhanced SPI */ @@ -487,34 +539,49 @@ #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME /* Default address of microcode for the Linux Fman driver */ -#define CONFIG_SYS_FMAN_FW #if defined(CONFIG_SPIFLASH) /* * env is stored at 0x100000, sector size is 0x10000, ucode is stored after * env, so we got 0x110000. */ -#define CONFIG_SYS_QE_FW_IN_SPIFLASH 0x110000 +#define CONFIG_SYS_QE_FW_IN_SPIFLASH +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is * about 545KB (1089 blocks), Env is stored after the image, and the env size is * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130. */ -#define CONFIG_SYS_QE_FW_IN_MMC (512 * 1130) +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC +#define CONFIG_SYS_QE_FMAN_FW_ADDR (512 * 1130) #elif defined(CONFIG_NAND) -#define CONFIG_SYS_QE_FW_IN_NAND (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#define CONFIG_SYS_QE_FMAN_FW_IN_NAND +#define CONFIG_SYS_QE_FMAN_FW_ADDR (6 * CONFIG_SYS_NAND_BLOCK_SIZE) +#elif defined(CONFIG_SRIOBOOT_SLAVE) +/* + * Slave has no ucode locally, it can fetch this from remote. When implementing + * in two corenet boards, slave's ucode could be stored in master's memory + * space, the address can be mapped from slave TLB->slave LAW-> + * slave SRIO outbound window->master inbound window->master LAW-> + * the ucode address in master's NOR flash. + */ +#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xFFE00000 #else -#define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000 +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xEF000000 #endif -#define CONFIG_SYS_FMAN_FW_LENGTH 0x10000 -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_FMAN_FW_LENGTH) +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_FMAN_ENET +#define CONFIG_PHYLIB_10G +#define CONFIG_PHY_VITESSE +#define CONFIG_PHY_TERANETICS #endif #ifdef CONFIG_PCI -#define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_E1000 @@ -580,6 +647,7 @@ #define CONFIG_CMD_MII #define CONFIG_CMD_PING #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO #ifdef CONFIG_PCI #define CONFIG_CMD_PCI @@ -597,8 +665,6 @@ #define CONFIG_CMD_EXT2 #define CONFIG_HAS_FSL_DR_USB -#define CONFIG_MMC - #ifdef CONFIG_MMC #define CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR @@ -644,8 +710,8 @@ /* * Environment Configuration */ -#define CONFIG_ROOTPATH /opt/nfsroot -#define CONFIG_BOOTFILE uImage +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ /* default location for tftp and bootm */ @@ -655,7 +721,7 @@ #define CONFIG_BAUDRATE 115200 -#if defined(CONFIG_P4080DS) +#if defined(CONFIG_P4080DS) || defined(CONFIG_P3060QDS) #define __USB_PHY_TYPE ulpi #else #define __USB_PHY_TYPE utmi @@ -708,4 +774,8 @@ #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT +#ifdef CONFIG_SECURE_BOOT +#include +#endif + #endif /* __CONFIG_H */