X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fcradle.h;h=c21af3817f431ea16b810348f31ba17c7fc079e2;hb=7842fb7c4f5be961c7aa9091dc8c760683b1377c;hp=5131175045fb98aaa2fb5b179d2188ab29353d29;hpb=156feb90d200f186cdfd856d7f6f1878bb1bec1e;p=u-boot

diff --git a/include/configs/cradle.h b/include/configs/cradle.h
index 5131175045..c21af3817f 100644
--- a/include/configs/cradle.h
+++ b/include/configs/cradle.h
@@ -37,16 +37,19 @@
 
 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff */
 
+/* we will never enable dcache, because we have to setup MMU first */
+#define CONFIG_SYS_NO_DCACHE
+#define	CONFIG_SYS_TEXT_BASE		0x0
 /*
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
  */
-#define CONFIG_DRIVER_SMC91111
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC91111
 #define CONFIG_SMC91111_BASE 0x10000300
 #define CONFIG_SMC91111_EXT_PHY
 #define CONFIG_SMC_USE_32_BIT
@@ -54,6 +57,7 @@
 /*
  * select serial console configuration
  */
+#define CONFIG_PXA_SERIAL
 #define CONFIG_FFUART          1       /* we use FFUART on LUBBOCK */
 
 /* allow to overwrite serial and ethaddr */
@@ -99,8 +103,6 @@
 #define CONFIG_SYS_MEMTEST_START       0xa0400000      /* memtest works on     */
 #define CONFIG_SYS_MEMTEST_END         0xa0800000      /* 4 ... 8 MB in DRAM   */
 
-#undef  CONFIG_SYS_CLKS_IN_HZ          /* everything, incl board info, in Hz */
-
 #define CONFIG_SYS_LOAD_ADDR           0xa2000000      /* default load address */
 
 #define CONFIG_SYS_HZ			1000
@@ -123,15 +125,9 @@
 /*
  * Physical Memory Map
  */
-#define CONFIG_NR_DRAM_BANKS    4          /* we have 2 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS    1          /* we have 1 bank of DRAM */
 #define PHYS_SDRAM_1            0xa0000000 /* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE       0x01000000 /* 64 MB */
-#define PHYS_SDRAM_2            0xa4000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE       0x00000000 /* 0 MB */
-#define PHYS_SDRAM_3            0xa8000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE       0x00000000 /* 0 MB */
-#define PHYS_SDRAM_4            0xac000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE       0x00000000 /* 0 MB */
 
 #define PHYS_FLASH_1            0x00000000 /* Flash Bank #1 */
 #define PHYS_FLASH_2            0x04000000 /* Flash Bank #1 */
@@ -142,6 +138,9 @@
 
 #define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
 /*
  * FLASH and environment organization
  */
@@ -283,9 +282,9 @@
  * Clocks, power control and interrupts
  */
 #define CONFIG_SYS_PSSR_VAL        0x00000020
-#define CONFIG_SYS_CCCR_VAL        0x00000141  /* 100 MHz memory, 200 MHz CPU  */
-#define CONFIG_SYS_CKEN_VAL        0x00000060  /* FFUART and STUART enabled    */
-#define CONFIG_SYS_ICMR_VAL        0x00000000  /* No interrupts enabled        */
+#define CONFIG_SYS_CCCR        0x00000141  /* 100 MHz memory, 200 MHz CPU  */
+#define CONFIG_SYS_CKEN        0x00000060  /* FFUART and STUART enabled    */
+#define CONFIG_SYS_ICMR        0x00000000  /* No interrupts enabled        */
 
 /* FIXME
  *
@@ -313,6 +312,8 @@
 #define CONFIG_SYS_MDMRS_VAL       0x00000000
 #define CONFIG_SYS_MDREFR_VAL      0x00403018  /* Initial setting, individual bits set in lowlevel_init.S */
 #endif
+#define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
+#define	CONFIG_SYS_SXCNFG_VAL		0x00000000
 
 /*
  * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
@@ -336,8 +337,6 @@
 #define LED_IRDA1 2
 #define LED_IRDA2 4
 #define LED_IRDA3 6
-#define CRADLE_LED_SET_REG GPSR2
-#define CRADLE_LED_CLR_REG GPCR2
 
 /* SuperIO defines */
 #define CRADLE_SIO_INDEX      0x2e