X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fcyrus.h;h=6ce2bc0042dd59443f1eb54f30d6d2054fbc03e0;hb=8730d012c9bd92d6412b3ef6e33b40c5df00f225;hp=5f5138acbb0e1869a9d41a6abcbb0983560f241a;hpb=cefe11cdb2a0d1fe0daf90408d3c49e627ef39a7;p=u-boot diff --git a/include/configs/cyrus.h b/include/configs/cyrus.h index 5f5138acbb..6ce2bc0042 100644 --- a/include/configs/cyrus.h +++ b/include/configs/cyrus.h @@ -1,19 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Based on corenet_ds.h - * - * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_CYRUS - -#if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_PPC_P5040) +#if !defined(CONFIG_ARCH_P5020) && !defined(CONFIG_ARCH_P5040) #error Must call Cyrus CONFIG with a specific CPU enabled. #endif -#define CONFIG_MMC #define CONFIG_SDCARD #define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE3 @@ -33,41 +29,28 @@ #if defined(CONFIG_ARCH_P5020) #define CONFIG_SYS_CLK_FREQ 133000000 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg -#elif defined(CONFIG_PPC_P5040) +#elif defined(CONFIG_ARCH_P5040) #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg #endif /* High Level Configuration Options */ -#define CONFIG_BOOKE -#define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_MP /* support multiple processors */ #define CONFIG_SYS_MMC_MAX_DEVICE 1 -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff40000 -#endif - #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS -#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_FSL_LAW /* Use common FSL init code */ - #define CONFIG_ENV_OVERWRITE -#define CONFIG_SYS_NO_FLASH - #if defined(CONFIG_SDCARD) #define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_ENV_IS_IN_MMC #define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 @@ -98,8 +81,6 @@ #undef CONFIG_POST #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 -#define CONFIG_SYS_ALT_MEMTEST -#define CONFIG_PANIC_HANG /* do not reset board on panic */ /* * Config the L3 Cache as L3 SRAM @@ -129,7 +110,6 @@ #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD -#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_SPD_BUS_NUM 1 #define SPD_EEPROM_ADDRESS1 0x51 @@ -171,8 +151,6 @@ #define CONFIG_SYS_RAMBOOT #endif -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ #define CONFIG_MISC_INIT_R #define CONFIG_HWCONFIG @@ -205,7 +183,6 @@ * open - index 2 * shorted - index 1 */ -#define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -250,7 +227,6 @@ #define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50 #define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa -#define CONFIG_CMD_DATE 1 #define CONFIG_RTC_MCP79411 1 #define CONFIG_SYS_RTC_BUS_NUM 3 #define CONFIG_SYS_I2C_RTC_ADDR 0x6f @@ -330,7 +306,6 @@ #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ /* Qman/Bman */ -#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ #define CONFIG_SYS_BMAN_NUM_PORTALS 10 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 #ifdef CONFIG_PHYS_64BIT @@ -379,23 +354,16 @@ #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_FMAN_ENET -#define CONFIG_PHY_MICREL -#define CONFIG_PHY_MICREL_KSZ9021 #endif #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_NET_MULTI #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_DOS_PARTITION #endif /* CONFIG_PCI */ /* SATA */ #ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_LIBATA -#define CONFIG_FSL_SATA - #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SATA1 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR @@ -405,15 +373,12 @@ #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA #define CONFIG_LBA48 -#define CONFIG_CMD_SATA -#define CONFIG_DOS_PARTITION #endif #ifdef CONFIG_FMAN_ENET #define CONFIG_SYS_TBIPA_VALUE 8 #define CONFIG_MII /* MII PHY management */ #define CONFIG_ETHPRIME "FM1@DTSEC4" -#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #endif /* @@ -422,17 +387,6 @@ #define CONFIG_LOADS_ECHO /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ -/* - * Command line configuration. - */ -#define CONFIG_CMD_ERRATA -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_REGINFO - -#ifdef CONFIG_PCI -#define CONFIG_CMD_PCI -#endif - /* * USB */ @@ -440,37 +394,21 @@ #define CONFIG_HAS_FSL_MPH_USB #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_EHCI_IS_TDI -#define CONFIG_SYS_USB_EVENT_POLL /* _VIA_CONTROL_EP */ #endif #ifdef CONFIG_MMC -#define CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT -#define CONFIG_GENERIC_MMC -#define CONFIG_DOS_PARTITION #endif /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ /* * For booting Linux, the board info and command line data @@ -494,9 +432,6 @@ /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 - -#define CONFIG_BAUDRATE 115200 - #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \