X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fdavinci_dm6467evm.h;h=2132342eb7e102b7ae846db901f1196dab35d1fa;hb=4a377552f01b7b19ea5fc02eb844c786751f7247;hp=f0a8e98c36a8fec7482b456fb5d55c8d8f0b8deb;hpb=e03f31697478e9edd523f34b1ed54b6ff2cb7242;p=u-boot

diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h
index f0a8e98c36..2132342eb7 100644
--- a/include/configs/davinci_dm6467evm.h
+++ b/include/configs/davinci_dm6467evm.h
@@ -1,20 +1,7 @@
 /*
  * Copyright (C) 2009 Texas Instruments Incorporated
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef __CONFIG_H
@@ -22,14 +9,24 @@
 
 /* Spectrum Digital TMS320DM6467 EVM board */
 #define DAVINCI_DM6467EVM
+#define CONFIG_SYS_USE_NAND
+#define CONFIG_SYS_NAND_SMALLPAGE
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
 
 /* SoC Configuration */
 #define CONFIG_ARM926EJS				/* arm926ejs CPU */
+
+/* Clock rates detection */
+#ifndef __ASSEMBLY__
+extern unsigned int davinci_arm_clk_get(void);
+#endif
+
+/* Arm Clock frequency    */
+#define CONFIG_SYS_CLK_FREQ	davinci_arm_clk_get()
+/* Timer Input clock freq */
+#define CONFIG_SYS_HZ_CLOCK		(CONFIG_SYS_CLK_FREQ/2)
 #define CONFIG_SYS_TIMERBASE		0x01c21400	/* use timer 0 */
-#define CONFIG_SYS_HZ_CLOCK		27000000
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SOC_DM646X
 
 /* EEPROM definitions for EEPROM */
@@ -43,7 +40,6 @@
 #define CONFIG_SYS_MEMTEST_START	0x80000000
 #define CONFIG_SYS_MEMTEST_END		0x81000000	/* 16MB RAM test */
 #define CONFIG_NR_DRAM_BANKS		1
-#define CONFIG_STACKSIZE		(256 << 10)	/* 256 KiB */
 #define PHYS_SDRAM_1			0x80000000	/* DDR Start */
 #define PHYS_SDRAM_1_SIZE		(256 << 20)	/* DDR size 256MB */
 
@@ -52,6 +48,7 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_SYS_BARGSIZE		1024		/* Bootarg Size */
 #define CONFIG_SYS_LOAD_ADDR		0x80700000	/* kernel address */
+#define CONFIG_REVISION_TAG
 
 /* Serial Driver info */
 #define CONFIG_SYS_NS16550
@@ -61,7 +58,6 @@
 #define CONFIG_SYS_NS16550_CLK		24000000
 #define CONFIG_CONS_INDEX		1
 #define CONFIG_BAUDRATE			115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /* I2C Configuration */
 #define CONFIG_HARD_I2C
@@ -69,6 +65,15 @@
 #define CONFIG_SYS_I2C_SPEED		80000
 #define CONFIG_SYS_I2C_SLAVE		10
 
+/* Network & Ethernet Configuration */
+#define CONFIG_DRIVER_TI_EMAC
+#define CONFIG_MII
+#define CONFIG_BOOTP_DNS
+#define CONFIG_BOOTP_DNS2
+#define CONFIG_BOOTP_SEND_HOSTNAME
+#define CONFIG_NET_RETRY_COUNT	10
+#define CONFIG_CMD_NET
+
 /* Flash & Environment */
 #define CONFIG_SYS_NO_FLASH
 #ifdef CONFIG_SYS_USE_NAND
@@ -87,7 +92,6 @@
 #endif
 
 /* U-Boot general configuration */
-#undef CONFIG_USE_IRQ				/* No IRQ/FIQ in U-Boot */
 #define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"uImage"	/* Boot file name */
 #define CONFIG_SYS_PROMPT	"DM6467 EVM > "	/* Monitor Command Prompt */
@@ -98,7 +102,6 @@
 #define CONFIG_VERSION_VARIABLE
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 #define CONFIG_CMDLINE_EDITING
 #define CONFIG_SYS_LONGHELP
 #define CONFIG_CRC32_VERIFY
@@ -116,7 +119,8 @@
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_SAVES
 #define CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_NET
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
 #undef CONFIG_CMD_BDI
 #undef CONFIG_CMD_FPGA
 #undef CONFIG_CMD_SETGETDCR
@@ -126,4 +130,16 @@
 #define CONFIG_CMD_NAND
 #endif
 
+#ifdef CONFIG_CMD_BDI
+#define CONFIG_CLOCKS
+#endif
+
+#define CONFIG_MAX_RAM_BANK_SIZE	(256 << 20)	/* 256 MB */
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_SIZE	0x1000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + \
+					 CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+
 #endif /* __CONFIG_H */