X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fdb-mv784mp-gp.h;h=567a4a7b94864282763ebf5e7833971a1f4f8780;hb=83d290c56fab2d38cd1ab4c4cc7099559c1d5046;hp=6ad5206fc04819050db045811890320a3664c77e;hpb=2218b32d88f9b4b4484cea9a8b034ddab0be298b;p=u-boot diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index 6ad5206fc0..567a4a7b94 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -1,7 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2014-2015 Stefan Roese - * - * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _CONFIG_DB_MV7846MP_GP_H @@ -12,22 +11,13 @@ */ #define CONFIG_DB_784MP_GP /* Board target name for DDR training */ -#define CONFIG_DISPLAY_BOARDINFO_LATE - /* * TEXT_BASE needs to be below 16MiB, since this area is scrubbed * for DDR ECC byte filling in the SPL before loading the main * U-Boot into it. */ -#define CONFIG_SYS_TEXT_BASE 0x00800000 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ -/* - * Commands configuration - */ -#define CONFIG_CMD_NAND -#define CONFIG_CMD_PCI - /* I2C */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MVTWSI @@ -51,17 +41,10 @@ #define CONFIG_PHY_MARVELL /* there is a marvell phy */ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -#define CONFIG_SYS_ALT_MEMTEST - /* SATA support */ #define CONFIG_SYS_SATA_MAX_DEVICE 2 -#define CONFIG_SATA_MV -#define CONFIG_LIBATA #define CONFIG_LBA48 -/* Additional FS support/configuration */ -#define CONFIG_SUPPORT_VFAT - /* PCIe support */ #ifndef CONFIG_SPL_BUILD #define CONFIG_PCI_MVEBU @@ -93,7 +76,6 @@ /* SPL */ /* Defines for SPL */ -#define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x40004030 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) @@ -108,7 +90,6 @@ #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) /* SPL related SPI defines */ -#define CONFIG_SPL_SPI_LOAD #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000 #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS