X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fdevkit8000.h;h=e72cee0c000db80a75290e53bfa3501bb26faf59;hb=ee422142f454d54f0ed39a2cbf083ff12e98a3e1;hp=182a1375dc3eeb733606f6a8a9f12785ab5f6649;hpb=875e4154921dcbd211c07316239121a97e9c74be;p=u-boot diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index 182a1375dc..e72cee0c00 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -33,29 +33,12 @@ #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ -#include /* get chip and board defs */ -#include - -#define CONFIG_SDRC /* The chip has SDRC controller */ #define CONFIG_NAND -#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ - /* to access nand at */ - /* CS0 */ /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ -#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 - -#include - -/* Display CPU and Board information */ -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 -/* Clock Defines */ -#define V_OSCK 26000000 /* Clock output from T2 */ -#define V_SCLK (V_OSCK >> 1) +#include #define CONFIG_MISC_INIT_R @@ -78,19 +61,6 @@ #define CONFIG_DM9000_NO_SROM 1 #undef CONFIG_DM9000_DEBUG -/* NS16550 Configuration */ -#define CONFIG_SYS_NS16550 -#define CONFIG_SYS_NS16550_SERIAL -#define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ - -/* select serial console configuration */ -#define CONFIG_CONS_INDEX 3 -#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 -#define CONFIG_SERIAL3 3 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} - /* SPI */ #undef CONFIG_SPI #undef CONFIG_OMAP3_SPI @@ -100,7 +70,6 @@ #define CONFIG_SYS_I2C_OMAP34XX /* TWL4030 */ -#define CONFIG_TWL4030_POWER 1 #define CONFIG_TWL4030_LED 1 /* Board NAND Info */ @@ -123,20 +92,11 @@ /* partition */ /* commands to include */ -#define CONFIG_CMD_DHCP /* DHCP support */ #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ #define CONFIG_CMD_NAND_LOCK_UNLOCK /* nand (un)lock commands */ -#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ -#undef CONFIG_CMD_IMI /* iminfo */ -#undef CONFIG_CMD_SPI -#undef CONFIG_CMD_GPIO -#undef CONFIG_CMD_ASKENV -#undef CONFIG_CMD_BOOTZ #undef CONFIG_SUPPORT_RAW_INITRD #undef CONFIG_FAT_WRITE -#undef CONFIG_CMD_EXT4 -#undef CONFIG_CMD_FS_GENERIC /* BOOTP/DHCP options */ #define CONFIG_BOOTP_SUBNETMASK @@ -217,7 +177,6 @@ "fi; " \ "else run nandboot; fi\0" - #define CONFIG_BOOTCOMMAND "run autoboot" /* Boot Argument Buffer Size */ @@ -225,16 +184,7 @@ #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ 0x01000000) /* 16MB */ -/* - * OMAP3 has 12 GP timers, they can be driven by the system clock - * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). - * This rate is divided by a local divisor. - */ -#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) - /* NAND and environment organization */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - #define CONFIG_ENV_IS_IN_NAND 1 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ @@ -245,19 +195,12 @@ #define CONFIG_SYS_SRAM_SIZE 0x10000 /* Defines for SPL */ -#define CONFIG_SPL_NAND_SIMPLE - -#define CONFIG_SPL_POWER_SUPPORT -#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" -#undef CONFIG_SPL_MTD_SUPPORT +#undef CONFIG_SPL_TEXT_BASE #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ -#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ -#undef CONFIG_SPL_STACK -#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK /* NAND boot config */ -#define CONFIG_SYS_NAND_BUSWIDTH_16BIT 16 +#define CONFIG_SYS_NAND_BUSWIDTH_16BIT #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_PAGE_SIZE 2048 @@ -287,6 +230,7 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x8 /* address 0x1000 */ #define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 8 /* 4KB */ +#undef CONFIG_SYS_SPL_ARGS_ADDR #define CONFIG_SYS_SPL_ARGS_ADDR (PHYS_SDRAM_1 + 0x100) #endif /* __CONFIG_H */