X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2FeNET.h;h=d5c9cad657abd8e7ced508b8e8aa7694f9335013;hb=d060b00eff2124ad841d72aff47de5d516ead242;hp=506f4c1c6933667b750bac12d20dca1841ad4070;hpb=cfbe861506e2dc3250ac99dc45bb3d1ac60f4857;p=u-boot

diff --git a/include/configs/eNET.h b/include/configs/eNET.h
index 506f4c1c69..d5c9cad657 100644
--- a/include/configs/eNET.h
+++ b/include/configs/eNET.h
@@ -33,7 +33,6 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_X86
 #define CONFIG_SYS_SC520
 #define CONFIG_SYS_SC520_SSI
 #define CONFIG_SHOW_BOOT_PROGRESS
@@ -106,6 +105,7 @@
 #define CONFIG_CMD_SETGETDCR
 #define CONFIG_CMD_SOURCE
 #define CONFIG_CMD_XIMG
+#define CONFIG_CMD_ZBOOT
 
 #define CONFIG_BOOTDELAY			15
 #define CONFIG_BOOTARGS				"root=/dev/mtdblock0 console=ttyS0,9600"
@@ -136,11 +136,11 @@
  * SDRAM Configuration
  */
 #define CONFIG_SYS_SDRAM_DRCTMCTL		0x18
+#define CONFIG_SYS_SDRAM_REFRESH_RATE		156
 #define CONFIG_NR_DRAM_BANKS			4
 
 /* CONFIG_SYS_SDRAM_DRCTMCTL Overrides the following*/
 #undef CONFIG_SYS_SDRAM_PRECHARGE_DELAY
-#undef CONFIG_SYS_SDRAM_REFRESH_RATE
 #undef CONFIG_SYS_SDRAM_RAS_CAS_DELAY
 #undef CONFIG_SYS_SDRAM_CAS_LATENCY_2T
 #undef CONFIG_SYS_SDRAM_CAS_LATENCY_3T
@@ -154,16 +154,30 @@
 #undef  CONFIG_SYS_GENERIC_TIMER
 #define CONFIG_SYS_PCAT_INTERRUPTS
 #define CONFIG_SYS_NUM_IRQS			16
+#define CONFIG_SYS_PC_BIOS
+#define CONFIG_SYS_PCI_BIOS
+#define CONFIG_SYS_X86_REALMODE
+#define CONFIG_SYS_X86_ISR_TIMER
 
 /*-----------------------------------------------------------------------
  * Memory organization:
  * 32kB Stack
+ * 16kB Cache-As-RAM @ 0x19200000
  * 256kB Monitor
+ * (128kB + Environment Sector Size) malloc pool
  */
-#define CONFIG_SYS_STACK_SIZE			0x8000
+#define CONFIG_SYS_STACK_SIZE			(32 * 1024)
+#define CONFIG_SYS_CAR_ADDR			0x19200000
+#define CONFIG_SYS_CAR_SIZE			(16 * 1024)
+#define CONFIG_SYS_INIT_SP_ADDR			(CONFIG_SYS_CAR_ADDR + \
+						 CONFIG_SYS_CAR_SIZE)
 #define CONFIG_SYS_MONITOR_BASE			CONFIG_SYS_TEXT_BASE
 #define CONFIG_SYS_MONITOR_LEN			(256 * 1024)
-#define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SIZE + 128*1024)
+#define CONFIG_SYS_MALLOC_LEN			(CONFIG_ENV_SECT_SIZE + \
+						 128*1024)
+/* Address of temporary Global Data */
+#define CONFIG_SYS_INIT_GD_ADDR			CONFIG_SYS_CAR_ADDR
+
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
@@ -191,17 +205,25 @@
 #define CONFIG_SYS_FLASH_LEGACY_512Kx8
 #define CONFIG_SYS_FLASH_ERASE_TOUT		2000	/* ms */
 #define CONFIG_SYS_FLASH_WRITE_TOUT		2000	/* ms */
+
 /*-----------------------------------------------------------------------
  * Environment configuration
+ * - Boot flash is 512kB with 64kB sectors
+ * - StrataFlash is 32MB with 128kB sectors
+ * - Redundant embedded environment is 25% of the Boot flash
+ * - Redundant StrataFlash environment is <1% of the StrataFlash
+ * - Environment is therefore located in StrataFlash
+ * - Primary copy is located in first sector of first flash
+ * - Redundant copy is located in second sector of first flash
+ * - Stack is only 32kB, so environment size is limited to 4kB
  */
 #define CONFIG_ENV_IS_IN_FLASH
 #define CONFIG_ENV_SECT_SIZE			0x20000
-#define CONFIG_ENV_SIZE				CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SIZE				0x01000
 #define CONFIG_ENV_ADDR				CONFIG_SYS_FLASH_BASE_1
-/* Redundant Copy */
 #define CONFIG_ENV_ADDR_REDUND			(CONFIG_SYS_FLASH_BASE_1 + \
 						 CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND			CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_SIZE_REDUND			CONFIG_ENV_SIZE
 
 /*-----------------------------------------------------------------------
  * PCI configuration
@@ -216,7 +238,6 @@
 /*-----------------------------------------------------------------------
  * Network device (TRL8100B) support
  */
-#define CONFIG_NET_MULTI
 #define CONFIG_RTL8139
 
 /*-----------------------------------------------------------------------
@@ -475,6 +496,22 @@
  */
 #define CONFIG_SYS_SC520_BOOTCS_PAR		0x8a01f800
 
+/*-----------------------------------------------------------------------
+ * Cache-As-RAM (Targets Boot Flash)
+ *
+ * 100 1 0 0 0 0001111 011001001000000000 }- 0x903d9200
+ * \ / | | | | \--+--/ \-------+--------/
+ *  |  | | | |    |            +------------ Start at 0x19200000
+ *  |  | | | |    +------------------------- 64k Region Size
+ *  |  | | | |                               ((15 + 1) * 4kB)
+ *  |  | | | +------------------------------ 4kB Page Size
+ *  |  | | +-------------------------------- Writes Enabled
+ *  |  | +---------------------------------- Caching Enabled
+ *  |  +------------------------------------ Execution Prevented
+ *  +--------------------------------------- BOOTCS
+ */
+#define CONFIG_SYS_SC520_CAR_PAR		0x903d9200
+
 /*-----------------------------------------------------------------------
  * PAR for Low Level I/O (LEDs, Hex Switches etc) - 33 Bytes @ 0x1000, GPCS6
  *