X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fexynos-common.h;h=3b61a4104d72b39c1da23d891f166b71ab8750b4;hb=2d221489df021393654805536be7effcb9d39702;hp=1f3ee55098fc8f8289cd882eceecbfa66b8147d6;hpb=f4e7e2d12164c3235c3f5e19a68a503623029d35;p=u-boot

diff --git a/include/configs/exynos-common.h b/include/configs/exynos-common.h
index 1f3ee55098..3b61a4104d 100644
--- a/include/configs/exynos-common.h
+++ b/include/configs/exynos-common.h
@@ -16,25 +16,18 @@
 #include <asm/arch/cpu.h>		/* get chip and board defs */
 #include <linux/sizes.h>
 
-#define CONFIG_SYS_GENERIC_BOARD
-#define CONFIG_DM
-#define CONFIG_CMD_DM
-#define CONFIG_DM_GPIO
-#define CONFIG_DM_SERIAL
-#define CONFIG_DM_SPI
-#define CONFIG_DM_SPI_FLASH
-
 #define CONFIG_ARCH_CPU_INIT
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_BOARD_EARLY_INIT_F
 
+#define CONFIG_USE_ARCH_MEMCPY
+#define CONFIG_USE_ARCH_MEMSET
+
 /* Keep L2 Cache Disabled */
-#define CONFIG_CMD_CACHE
 
 /* input clock of PLL: 24MHz input clock */
 #define CONFIG_SYS_CLK_FREQ		24000000
+#define CONFIG_TIMER_CLK_FREQ		CONFIG_SYS_CLK_FREQ
 
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_CMDLINE_TAG
@@ -42,7 +35,6 @@
 #define CONFIG_ENV_OVERWRITE
 
 /* Size of malloc() pool before and after relocation */
-#define CONFIG_SYS_MALLOC_F_LEN		(1 << 10)
 #define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (80 << 20))
 
 /* select serial console configuration */
@@ -57,18 +49,11 @@
 #define CONFIG_EXYNOS_DWMMC
 #define CONFIG_BOUNCE_BUFFER
 
-#define CONFIG_ZERO_BOOTDELAY_CHECK
-
 /* PWM */
 #define CONFIG_PWM
 
 /* Command definition*/
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_MMC
-#define CONFIG_CMD_EXT4_WRITE
 #define CONFIG_FAT_WRITE
-#define CONFIG_CMD_FS_GENERIC
 
 #define CONFIG_CMD_PART
 #define CONFIG_PARTITION_UUIDS
@@ -83,7 +68,6 @@
 
 /* FLASH and environment organization */
 #define CONFIG_SYS_NO_FLASH
-#undef CONFIG_CMD_IMLS
 
 #include <config_distro_defaults.h>