X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fgdppc440etx.h;h=7b8bac48ec7149ea124786d1cc86a1daeaaa6f69;hb=f9c1456cf632175afb7d6b27f42f1aab8432be0f;hp=282afbcc6100e24cacfb0362166ff9a5081e6bcb;hpb=d48455ad8cefd25d7b49f68fd16d0e9fd551732a;p=u-boot

diff --git a/include/configs/gdppc440etx.h b/include/configs/gdppc440etx.h
index 282afbcc61..7b8bac48ec 100644
--- a/include/configs/gdppc440etx.h
+++ b/include/configs/gdppc440etx.h
@@ -50,6 +50,10 @@
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* call board_early_init_f*/
 #define CONFIG_MISC_INIT_R		1	/* call misc_init_r()     */
 
+#undef CONFIG_ZERO_BOOTDELAY_CHECK     /* ignore keypress on bootdelay==0 */
+#define CONFIG_AUTOBOOT_KEYED          /* use key strings to stop autoboot */
+#define CONFIG_AUTOBOOT_STOP_STR " "
+
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
@@ -72,10 +76,9 @@
  */
 #define CONFIG_SYS_INIT_RAM_DCACHE	1		/* d-cache as init ram*/
 #define CONFIG_SYS_INIT_RAM_ADDR	0x70000000	/* DCache             */
-#define CONFIG_SYS_INIT_RAM_END		(4 << 10)
-#define CONFIG_SYS_GBL_DATA_SIZE	256		/* num bytes init data*/
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END \
-					 - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE		(4 << 10)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE \
+					 - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
@@ -175,6 +178,7 @@
 
 /* General PCI */
 #define CONFIG_PCI				/* include pci support        */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
 #undef  CONFIG_PCI_PNP				/* do (not) pci plug-and-play */
 #define CONFIG_PCI_SCAN_SHOW			/* show pci devices on startup*/
 #define CONFIG_SYS_PCI_TARGBASE		0x80000000	/* PCIaddr mapped to \