X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Ficon.h;h=2fac0efe13051902c9946497bc4678371b963e5a;hb=810c44274980d8bb9fa0d81d091a374adbae8309;hp=3a57d695f9e4f661a9ad963c195722c7be02dfa8;hpb=0903b524abd3abfb1e4c3197ba6652bd8c98fe9a;p=u-boot

diff --git a/include/configs/icon.h b/include/configs/icon.h
index 3a57d695f9..2fac0efe13 100644
--- a/include/configs/icon.h
+++ b/include/configs/icon.h
@@ -35,6 +35,9 @@
 #define CONFIG_4xx		1		/* ... PPC4xx family	*/
 #define CONFIG_440		1		/* ... PPC440 family	*/
 #define CONFIG_440SPE		1		/* Specifc SPe support	*/
+
+#define	CONFIG_SYS_TEXT_BASE	0xFFFA0000
+
 #define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
 #define CONFIG_SYS_4xx_RESET_TYPE 0x2	/* use chip reset on this board	*/
 
@@ -52,7 +55,6 @@
  * actual resources get mapped (not physical addresses)
  */
 #define CONFIG_SYS_FLASH_BASE	0xfc000000	/* later mapped to this addr */
-#define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000	/* internal peripherals	*/
 #define CONFIG_SYS_ISRAM_BASE	0x90000000	/* internal SRAM	*/
 
 #define CONFIG_SYS_PCI_MEMBASE	0x80000000	/* mapped PCI memory	*/
@@ -95,18 +97,16 @@
 #define CONFIG_SYS_TEMP_STACK_OCM	1
 #define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_ISRAM_BASE
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE	/* Init RAM */
-#define CONFIG_SYS_INIT_RAM_END		0x2000		/* end used area */
-#define CONFIG_SYS_GBL_DATA_SIZE	128		/* sizeof init data */
+#define CONFIG_SYS_INIT_RAM_SIZE	0x2000		/* size of used area */
 
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
-					 CONFIG_SYS_GBL_DATA_SIZE)
-#define CONFIG_SYS_POST_WORD_ADDR	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_POST_WORD_ADDR
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 
 /*
  * Serial Port
  */
-#undef CONFIG_UART1_CONSOLE
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
 #undef CONFIG_SYS_EXT_SERIAL_CLOCK
 
 /*
@@ -142,6 +142,26 @@
 #define CONFIG_SYS_I2C_RTC_ADDR	0x68
 #define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux	*/
 
+/*
+ * Video options
+ */
+#define CONFIG_VIDEO
+
+#ifdef CONFIG_VIDEO
+#define CONFIG_VIDEO_SM501
+#define CONFIG_VIDEO_SM501_32BPP
+#define CONFIG_VIDEO_SM501_PCI
+#define VIDEO_FB_LITTLE_ENDIAN
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VIDEO_LOGO
+#define CONFIG_CONSOLE_EXTRA_INFO
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#define CONFIG_VIDEO_SW_CURSOR
+#define CONFIG_VIDEO_BMP_RLE8
+#define CONFIG_SPLASH_SCREEN
+#define CFG_CONSOLE_IS_IN_ENV
+#endif
+
 /*
  * Environment
  */
@@ -171,6 +191,9 @@
 #define CONFIG_CMD_PCI
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_SNTP
+#ifdef CONFIG_VIDEO
+#define CONFIG_CMD_BMP
+#endif
 
 #define	CONFIG_IBM_EMAC4_V4		/* 440SPe has this EMAC version	*/
 #define CONFIG_PHY_ADDR		1	/* PHY address, See schematics	*/