X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fintegratorap.h;h=a1fdbb8140afa6257ef26365c893de355d0a3f8e;hb=ed97abed27455b4f9e0dec6274976f5010258ed9;hp=ad92f3209bdbb347b3975401c1a192e1a0c5dc57;hpb=716c1dcb41389e865af1edde2ca15f2c567984cf;p=u-boot diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index ad92f3209b..a1fdbb8140 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -30,69 +30,88 @@ #ifndef __CONFIG_H #define __CONFIG_H + +#define CONFIG_INTEGRATOR +#define CONFIG_ARCH_INTEGRATOR /* * High Level Configuration Options * (easy to change) */ -#define CFG_MEMTEST_START 0x100000 -#define CFG_MEMTEST_END 0x10000000 -#define CFG_HZ 1000 -#define CFG_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */ -#define CFG_TIMERBASE 0x13000100 /* Timer1 */ +#define CONFIG_SYS_TEXT_BASE 0x01000000 +#define CONFIG_SYS_MEMTEST_START 0x100000 +#define CONFIG_SYS_MEMTEST_END 0x10000000 +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */ +#define CONFIG_SYS_TIMERBASE 0x13000100 /* Timer1 */ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ -#undef CONFIG_INIT_CRITICAL +#define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_CM_INIT 1 #define CONFIG_CM_REMAP 1 -#undef CONFIG_CM_SPD_DETECT +#define CONFIG_CM_SPD_DETECT /* * Size of malloc() pool */ -#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* * PL010 Configuration */ -#define CFG_PL010_SERIAL +#define CONFIG_PL010_SERIAL #define CONFIG_CONS_INDEX 0 #define CONFIG_BAUDRATE 38400 -#define CONFIG_PL01x_PORTS { (void *) (CFG_SERIAL0), (void *) (CFG_SERIAL1) } -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } -#define CFG_SERIAL0 0x16000000 -#define CFG_SERIAL1 0x17000000 +#define CONFIG_PL01x_PORTS { (void *) (CONFIG_SYS_SERIAL0), (void *) (CONFIG_SYS_SERIAL1) } +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_SYS_SERIAL0 0x16000000 +#define CONFIG_SYS_SERIAL1 0x17000000 + -/*#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_PCI) */ -/*#define CONFIG_NET_MULTI */ -/*#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */ +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY) +/* + * Command line configuration. + */ + + +#define CONFIG_CMD_IMI +#define CONFIG_CMD_BDI +#define CONFIG_CMD_BOOTD +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_IMLS +#define CONFIG_CMD_LOADB +#define CONFIG_CMD_LOADS -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include #define CONFIG_BOOTDELAY 2 -#define CONFIG_BOOTARGS "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty" +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 console=ttyAM0 console=tty" #define CONFIG_BOOTCOMMAND "" /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "Integrator-AP # " /* Monitor Command Prompt */ -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "Integrator-AP # " /* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "# " +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ -#define CFG_LOAD_ADDR 0x7fc0 /* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x7fc0 /* default load address */ /*----------------------------------------------------------------------- * Stack sizes @@ -111,35 +130,40 @@ #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ #define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_SIZE PHYS_SDRAM_1_SIZE +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET -#define CFG_FLASH_BASE 0x24000000 +#define CONFIG_SYS_FLASH_BASE 0x24000000 /*----------------------------------------------------------------------- * FLASH and environment organization */ -#define CFG_ENV_IS_NOWHERE -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ +#define CONFIG_SYS_FLASH_CFI 1 +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ /* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ -#define CFG_MAX_FLASH_SECT 128 -#define CFG_ENV_SIZE 32768 +#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ +#define CONFIG_SYS_MAX_FLASH_SECT 128 +#define CONFIG_ENV_SIZE 32768 -#define PHYS_FLASH_1 (CFG_FLASH_BASE) /*----------------------------------------------------------------------- * PCI definitions */ -/*#define CONFIG_PCI /--* include pci support */ +#ifdef CONFIG_PCI /* pci support */ #undef CONFIG_PCI_PNP #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ #define DEBUG #define CONFIG_EEPRO100 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ - +#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define INTEGRATOR_BOOT_ROM_BASE 0x20000000 #define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 @@ -268,6 +292,7 @@ #define INTEGRATOR_SC_PCIENABLE \ (INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET) +#endif /* CONFIG_PCI */ /*----------------------------------------------------------------------- * There are various dependencies on the core module (CM) fitted * Users should refer to their CM user guide @@ -275,42 +300,6 @@ * to define the necessary CONFIG_ s for the CM involved * see e.g. integratorcp_CM926EJ-S_config */ +#include "armcoremodule.h" -#define CM_BASE 0x10000000 - -/* CM registers common to all integrator/CP CMs */ -#define OS_CTRL 0x0000000C -#define CMMASK_REMAP 0x00000005 /* Set remap & led */ -#define CMMASK_RESET 0x00000008 -#define OS_LOCK 0x00000014 -#define CMVAL_LOCK 0x0000A000 /* Locking value */ -#define CMMASK_LOCK 0x0000005F /* Locking value */ -#define CMVAL_UNLOCK 0x00000000 /* Any value != CM_LOCKVAL */ -#define OS_SDRAM 0x00000020 -#define OS_INIT 0x00000024 -#define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */ -#define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */ -#define CMMASK_LOWVEC 0x00000004 /* vectors @ 0x00000000 */ - -#ifdef CONFIG_CM_SPD_DETECT -#define OS_SPD 0x00000100 /* The SDRAM SPD data is copied here */ -#endif - -#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E) -#define CMMASK_INIT_102 0x00000300 /* see CM102xx ref manual - * - PLL test clock bypassed - * - bus clock ratio 2 - * - little endian - * - vectors at zero - */ -#endif /* CM1022xx */ - -#define CMMASK_LE 0x00000008 /* little endian */ -#define CMMASK_CMxx6_COMMON 0x00000100 /* Common value for CMxx6 - * - divisor/ratio b00000001 - * bx - * - HCLKDIV b000 - * bxx - * - PLL BYPASS b00 - */ #endif /* __CONFIG_H */