X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fintegratorap.h;h=e0e82583410516c1c0f4fca9a6da2aaf8821d3bb;hb=5d8e359c38d3ab80015e47d0cab792efe75cacf9;hp=6ce3b4dc014ed2063677d9fb9e618a1eb9441ec1;hpb=f82642e33899766892499b163e60560fbbf87773;p=u-boot

diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h
index 6ce3b4dc01..e0e8258341 100644
--- a/include/configs/integratorap.h
+++ b/include/configs/integratorap.h
@@ -44,7 +44,7 @@
 #define CONFIG_SETUP_MEMORY_TAGS	1
 #define CONFIG_MISC_INIT_R	1	/* call misc_init_r during start up */
 
-#undef CONFIG_INIT_CRITICAL
+#define CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_CM_INIT		1
 #define CONFIG_CM_REMAP		1
 #undef CONFIG_CM_SPD_DETECT
@@ -102,7 +102,6 @@
 #define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
 #define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
 #define CONFIG_SYS_LOAD_ADDR	0x7fc0	/* default load address */
 
 /*-----------------------------------------------------------------------
@@ -123,27 +122,27 @@
 #define PHYS_SDRAM_1		0x00000000	/* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE	0x02000000	/* 32 MB */
 
-#define CONFIG_SYS_FLASH_BASE		0x24000000
+#define CONFIG_SYS_FLASH_BASE	0x24000000
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
+#define CONFIG_SYS_FLASH_CFI		1
+#define CONFIG_FLASH_CFI_DRIVER		1
 #define CONFIG_ENV_IS_NOWHERE
 #define CONFIG_SYS_MAX_FLASH_BANKS	1		/* max number of memory banks */
-#define PHYS_FLASH_SIZE		0x01000000	/* 16MB */
 /* timeout values are in ticks */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Erase */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	(2*CONFIG_SYS_HZ)	/* Timeout for Flash Write */
 #define CONFIG_SYS_MAX_FLASH_SECT	128
-#define CONFIG_ENV_SIZE		32768
+#define CONFIG_ENV_SIZE			32768
 
-#define PHYS_FLASH_1		(CONFIG_SYS_FLASH_BASE)
 
 /*-----------------------------------------------------------------------
  * PCI definitions
  */
 
-/*#define CONFIG_PCI			/--* include pci support	*/
+#ifdef CONFIG_PCI			/* pci support	*/
 #undef CONFIG_PCI_PNP
 #define CONFIG_PCI_SCAN_SHOW	1	/* show pci devices on startup	*/
 #define DEBUG
@@ -151,7 +150,6 @@
 #define CONFIG_EEPRO100
 #define CONFIG_SYS_RX_ETH_BUFFER	8	/* use 8 rx buffer on eepro100	*/
 
-
 #define INTEGRATOR_BOOT_ROM_BASE	0x20000000
 #define INTEGRATOR_HDR0_SDRAM_BASE	0x80000000
 
@@ -279,6 +277,7 @@
 #define INTEGRATOR_SC_PCIENABLE \
 			(INTEGRATOR_SC_BASE + INTEGRATOR_SC_PCIENABLE_OFFSET)
 
+#endif /* CONFIG_PCI */
 /*-----------------------------------------------------------------------
  * There are various dependencies on the core module (CM) fitted
  * Users should refer to their CM user guide