X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fiocon.h;h=8bc89a05eb8b40701e39114d8753003dd7600428;hb=0a34a5fd2794a87c43e8d009ccb711e6839843b2;hp=f36c2a3504e442f718bba1843bcaaf79d8b6fca1;hpb=7d2357c1999ff1f93f795282526230a8bd176106;p=u-boot

diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index f36c2a3504..8bc89a05eb 100644
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -17,9 +17,12 @@
  * Include common defines/options for all AMCC eval boards
  */
 #define CONFIG_HOSTNAME		iocon
-#define CONFIG_IDENT_STRING	" iocon 0.05"
+#define CONFIG_IDENT_STRING	" iocon 0.06"
 #include "amcc-common.h"
 
+/* Reclaim some space. */
+#undef CONFIG_SYS_LONGHELP
+
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_EARLY_INIT_R
 #define CONFIG_LAST_STAGE_INIT
@@ -33,12 +36,9 @@
 #define PLLMR1_DEFAULT PLLMR1_266_133_66
 
 #undef CONFIG_ZERO_BOOTDELAY_CHECK	/* ignore keypress on bootdelay==0 */
-#define CONFIG_AUTOBOOT_KEYED		/* use key strings to stop autoboot */
-#define CONFIG_AUTOBOOT_STOP_STR " "
 
 /* new uImage format support */
-#define CONFIG_FIT
-#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+#define CONFIG_FIT_DISABLE_SHA256
 
 #define CONFIG_ENV_IS_IN_FLASH	/* use FLASH for environment vars */
 
@@ -64,6 +64,8 @@
 #define CONFIG_CMD_CACHE
 #define CONFIG_CMD_FPGAD
 #undef CONFIG_CMD_EEPROM
+#undef CONFIG_CMD_I2C
+#undef CONFIG_CMD_IRQ
 
 /*
  * SDRAM configuration (please see cpu/ppc/sdram.[ch])
@@ -99,12 +101,27 @@
 #define CONFIG_SYS_I2C_PPC4XX_CH0
 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
+#define CONFIG_SYS_I2C_IHS
 
 #define CONFIG_SYS_I2C_SPEED		400000
+#define CONFIG_SYS_SPD_BUS_NUM		4
 
 #define CONFIG_PCA953X			/* NXP PCA9554 */
 #define CONFIG_PCA9698			/* NXP PCA9698 */
 
+#define CONFIG_SYS_I2C_IHS_CH0
+#define CONFIG_SYS_I2C_IHS_SPEED_0		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_0		0x7F
+#define CONFIG_SYS_I2C_IHS_CH1
+#define CONFIG_SYS_I2C_IHS_SPEED_1		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_1		0x7F
+#define CONFIG_SYS_I2C_IHS_CH2
+#define CONFIG_SYS_I2C_IHS_SPEED_2		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_2		0x7F
+#define CONFIG_SYS_I2C_IHS_CH3
+#define CONFIG_SYS_I2C_IHS_SPEED_3		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_3		0x7F
+
 /*
  * Software (bit-bang) I2C driver configuration
  */
@@ -121,7 +138,9 @@
 #define CONFIG_SYS_I2C_SOFT_SPEED_4		50000
 #define CONFIG_SYS_I2C_SOFT_SLAVE_4		0x7F
 
-#define CONFIG_SYS_CH7301_I2C			{1, 2, 3, 4}
+#define CONFIG_SYS_ICS8N3QV01_I2C		{5, 6, 7, 8}
+#define CONFIG_SYS_CH7301_I2C			{5, 6, 7, 8}
+#define CONFIG_SYS_DP501_I2C			{0, 1, 2, 3}
 
 #ifndef __ASSEMBLY__
 void fpga_gpio_set(unsigned int bus, int pin);
@@ -149,12 +168,6 @@ int fpga_gpio_get(unsigned int bus, int pin);
 	} while (0)
 #define I2C_DELAY	udelay(25)	/* 1/4 I2C clock duration */
 
-/*
- * OSD hardware
- */
-#define CONFIG_SYS_MPC92469AC
-#define CONFIG_SYS_CH7301
-
 /*
  * FLASH organization
  */
@@ -283,8 +296,9 @@ int fpga_gpio_get(unsigned int bus, int pin);
  * OSD Setup
  */
 #define CONFIG_SYS_MPC92469AC
-#define CONFIG_SYS_CH7301
 #define CONFIG_SYS_OSD_SCREENS		1
+#define CONFIG_SYS_DP501_DIFFERENTIAL
+#define CONFIG_SYS_DP501_VCAPCTRL0	0x01 /* DDR mode 0, DE for H/VSYNC */
 
 #define CONFIG_BITBANGMII		/* bit-bang MII PHY management */
 #define CONFIG_BITBANGMII_MULTI