X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fiocon.h;h=9fcc6430cd3c58370637880e7fcee64d9605312b;hb=30f3413ef2629ede59e63e0a84f69a70748c09a6;hp=5e61b11372a6bc98da033717549f6ea5cc32424e;hpb=a605ea7e8322000d99a890d3173748f62ccb8549;p=u-boot

diff --git a/include/configs/iocon.h b/include/configs/iocon.h
index 5e61b11372..9fcc6430cd 100644
--- a/include/configs/iocon.h
+++ b/include/configs/iocon.h
@@ -130,6 +130,12 @@ int fpga_gpio_get(int pin);
 			else fpga_gpio_clear(0x0020)
 #define I2C_DELAY	udelay(25)	/* 1/4 I2C clock duration */
 
+/*
+ * OSD hardware
+ */
+#define CONFIG_SYS_MPC92469AC
+#define CONFIG_SYS_CH7301
+
 /*
  * FLASH organization
  */
@@ -231,13 +237,15 @@ int fpga_gpio_get(int pin);
 #define CONFIG_SYS_EBC_PB1AP		0x92015480
 #define CONFIG_SYS_EBC_PB1CR		0xFB858000
 
-/* Memory Bank 2 (FPGA) initialization */
-#define CONFIG_SYS_FPGA_BASE		0x7f100000
+/* Memory Bank 2 (FPGA0) initialization */
+#define CONFIG_SYS_FPGA0_BASE		0x7f100000
 #define CONFIG_SYS_EBC_PB2AP		0x02825080
-#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FPGA_BASE | 0x1a000)
+#define CONFIG_SYS_EBC_PB2CR		(CONFIG_SYS_FPGA0_BASE | 0x1a000)
+
+#define CONFIG_SYS_FPGA_BASE(k)		CONFIG_SYS_FPGA0_BASE
+#define CONFIG_SYS_FPGA_DONE(k)		0x0010
 
-#define CONFIG_SYS_FPGA_RFL_LOW		0x0000
-#define CONFIG_SYS_FPGA_RFL_HIGH	0x00fe
+#define CONFIG_SYS_FPGA_COUNT		1
 
 /* Memory Bank 3 (Latches) initialization */
 #define CONFIG_SYS_LATCH_BASE		0x7f200000
@@ -249,4 +257,11 @@ int fpga_gpio_get(int pin);
 #define CONFIG_SYS_LATCH1_RESET		0xffff
 #define CONFIG_SYS_LATCH1_BOOT		0xffff
 
+/*
+ * OSD Setup
+ */
+#define CONFIG_SYS_MPC92469AC
+#define CONFIG_SYS_CH7301
+#define CONFIG_SYS_OSD_SCREENS		CONFIG_SYS_FPGA_COUNT
+
 #endif	/* __CONFIG_H */