X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fipek01.h;h=ba08d92e354653662febc511de1cf3a9daaa2ce0;hb=d2d945714daeaabeaf83ddc63a1c938d9f98ee21;hp=6903b3614659661ea3ac9b51542e8cb9a438e3d5;hpb=859500a2be94bfa77a845b9c8a4c499587035fd5;p=u-boot

diff --git a/include/configs/ipek01.h b/include/configs/ipek01.h
index 6903b36146..ba08d92e35 100644
--- a/include/configs/ipek01.h
+++ b/include/configs/ipek01.h
@@ -37,13 +37,12 @@
 #define CONFIG_MPC5200_DDR	1	/* ... use DDR RAM */
 #define CONFIG_IPEK01           	/* Motherboard is ipek01 */
 
+#define	CONFIG_SYS_TEXT_BASE	0xfc000000
+
 #define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33MHz */
 
 #define CONFIG_MISC_INIT_R
 
-#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
-#define BOOTFLAG_WARM		0x02	/* Software reboot */
-
 #define CONFIG_SYS_CACHELINE_SIZE	32 /* For MPC5xxx CPUs */
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_SYS_CACHELINE_SHIFT	5  /* log base 2 of the above value */
@@ -265,16 +264,13 @@
 /* Use SRAM until RAM will be available */
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
 /* End of used area in DPRAM */
-#define CONFIG_SYS_INIT_RAM_END		MPC5XXX_SRAM_SIZE
-
-/* size in bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	128
+#define CONFIG_SYS_INIT_RAM_SIZE		MPC5XXX_SRAM_SIZE
 
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - \
-					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					 GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
-#define CONFIG_SYS_MONITOR_BASE		TEXT_BASE
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 #   define CONFIG_SYS_RAMBOOT		1
 #endif