X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fkm%2Fkm83xx-common.h;h=ae6b6dcf246c27d2bb1837bd21986d88c2784b64;hb=f13ac7b2f0ab02d8536a5baf793a3227274388a2;hp=0d411c2a4eeb78f3a57a6246b2279f6667fc386d;hpb=72cd4087c9644812b0fff9440e88e986d259bf41;p=u-boot

diff --git a/include/configs/km/km83xx-common.h b/include/configs/km/km83xx-common.h
index 0d411c2a4e..ae6b6dcf24 100644
--- a/include/configs/km/km83xx-common.h
+++ b/include/configs/km/km83xx-common.h
@@ -2,10 +2,7 @@
  * (C) Copyright 2010
  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef __CONFIG_KM83XX_H
@@ -15,13 +12,18 @@
 #include "keymile-common.h"
 #include "km-powerpc.h"
 
-#define MTDIDS_DEFAULT		"nor0=boot"
-#define MTDPARTS_DEFAULT	"mtdparts="			\
+#ifndef MTDIDS_DEFAULT
+# define MTDIDS_DEFAULT	"nor0=boot"
+#endif /* MTDIDS_DEFAULT */
+
+#ifndef MTDPARTS_DEFAULT
+# define MTDPARTS_DEFAULT	"mtdparts="			\
 	"boot:"							\
 		"768k(u-boot),"					\
 		"128k(env),"					\
 		"128k(envred),"					\
-		"-(" CONFIG_KM_UBI_PARTITION_NAME ")"
+		"-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
+#endif /* MTDPARTS_DEFAULT */
 
 #define CONFIG_MISC_INIT_R
 /*
@@ -49,6 +51,8 @@
  */
 #define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE2	(CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
+
 #define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
 					DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
@@ -80,7 +84,6 @@
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	0x100 /* num bytes initial data */
 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
 						GENERATED_GBL_DATA_SIZE)
 
@@ -103,16 +106,17 @@
 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 
 #define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_LBLAWAR0_PRELIM	0x8000001b /* 256MB window size */
+#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_256MB)
 
 #define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE | \
-				(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
+				BR_PS_16 | /* 16 bit port size */ \
+				BR_MS_GPCM | /* MSEL = GPCM */ \
 				BR_V)
 
 #define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
 				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 				OR_GPCM_SCY_5 | \
-				OR_GPCM_TRLX | OR_GPCM_EAD)
+				OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS	1   /* max num of flash banks	*/
 #define CONFIG_SYS_MAX_FLASH_SECT	512 /* max num of sects on one chip */
@@ -123,15 +127,16 @@
  */
 /* Window base at flash base */
 #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_KMBEC_FPGA_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000001A /* 128MB window size */
+#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_128MB)
 
 #define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_KMBEC_FPGA_BASE | \
-				(1 << BR_PS_SHIFT) | /* 8 bit port size */ \
+				BR_PS_8 | /* 8 bit port size */ \
+				BR_MS_GPCM | /* MSEL = GPCM */ \
 				BR_V)
 #define CONFIG_SYS_OR1_PRELIM	(MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
 				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 				OR_GPCM_SCY_2 | \
-				OR_GPCM_TRLX | OR_GPCM_EAD)
+				OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 /*
  * Serial Port
@@ -156,8 +161,10 @@
 #define CONFIG_UEC_ETH
 #define CONFIG_ETHPRIME		"UEC0"
 
+#if !defined(CONFIG_MPC8309)
 #define CONFIG_UEC_ETH1		/* GETH1 */
 #define UEC_VERBOSE_DEBUG	1
+#endif
 
 #ifdef CONFIG_UEC_ETH1
 #define CONFIG_SYS_UEC1_UCC_NUM	3	/* UCC4 */
@@ -193,19 +200,30 @@
 #endif /* CFG_SYS_RAMBOOT */
 
 /* I2C */
-#define CONFIG_HARD_I2C		/* I2C with hardware support */
-#define CONFIG_FSL_I2C
-#define CONFIG_SYS_I2C_SPEED	200000	/* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE	0x7F
-#define CONFIG_SYS_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_NUM_I2C_BUSES	4
+#define CONFIG_SYS_I2C_MAX_HOPS		1
+#define CONFIG_SYS_I2C_FSL
+#define CONFIG_SYS_FSL_I2C_SPEED	200000
+#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
+#define CONFIG_SYS_I2C_OFFSET		0x3000
+#define CONFIG_SYS_FSL_I2C2_SPEED	200000
+#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
+#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100
+#define CONFIG_SYS_I2C_BUSES	{{0, {I2C_NULL_HOP} }, \
+		{0, {{I2C_MUX_PCA9547, 0x70, 2} } }, \
+		{0, {{I2C_MUX_PCA9547, 0x70, 1} } }, \
+		{1, {I2C_NULL_HOP} } }
+
+#define CONFIG_KM_IVM_BUS		2	/* I2C2 (Mux-Port 1)*/
 
 /* I2C SYSMON (LM75, AD7414 is almost compatible) */
 #define CONFIG_DTT_LM75		/* ON Semi's LM75 */
 #define CONFIG_DTT_SENSORS	{0, 1, 2, 3}	/* Sensor addresses */
 #define CONFIG_SYS_DTT_MAX_TEMP	70
-#define CONFIG_SYS_DTT_LOW_TEMP	-30
 #define CONFIG_SYS_DTT_HYSTERESIS	3
-#define CONFIG_SYS_DTT_BUS_NUM		(CONFIG_SYS_MAX_I2C_BUS)
+#define CONFIG_SYS_DTT_BUS_NUM		1
 
 #if defined(CONFIG_CMD_NAND)
 #define CONFIG_NAND_KMETER1
@@ -301,8 +319,6 @@
 #define CONFIG_EXTRA_ENV_SETTINGS \
 	CONFIG_KM_DEF_ENV						\
 	CONFIG_KM_DEF_ARCH						\
-	"dtt_bus=pca9547:70:a\0"					\
-	"EEprom_ivm=pca9547:70:9\0"					\
 	"newenv="							\
 		"prot off 0xF00C0000 +0x40000 && "			\
 		"era 0xF00C0000 +0x40000\0"				\