X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fkm%2Fkmp204x-common.h;h=3ae751eca52a5284f395028d817b6367a39a256b;hb=e883ffe00b6db807544c70e743cf7832d5d56d40;hp=f557ee2117ac8db03946ae2c0f8b2d8140941ced;hpb=ec1eaad06551e2422baf8743f6987d4f561f2ce6;p=u-boot diff --git a/include/configs/km/kmp204x-common.h b/include/configs/km/kmp204x-common.h index f557ee2117..3ae751eca5 100644 --- a/include/configs/km/kmp204x-common.h +++ b/include/configs/km/kmp204x-common.h @@ -1,17 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * (C) Copyright 2013 Keymile AG * Valentin Longchamp - * - * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _CONFIG_KMP204X_H #define _CONFIG_KMP204X_H -#define CONFIG_PPC_P2041 - -#define CONFIG_SYS_TEXT_BASE 0xfff40000 - #define CONFIG_KM_DEF_NETDEV "netdev=eth0\0" /* an additionnal option is required for UBI as subpage access is @@ -31,16 +26,12 @@ #define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg /* High Level Configuration Options */ -#define CONFIG_BOOKE -#define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ #define CONFIG_MP /* support multiple processors */ #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS -#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ @@ -48,11 +39,8 @@ #define CONFIG_SYS_DPAA_RMAN /* RMan */ -#define CONFIG_FSL_LAW /* Use common FSL init code */ - /* Environment in SPI Flash */ #define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_ENV_IS_IN_SPI_FLASH #define CONFIG_ENV_SPI_BUS 0 #define CONFIG_ENV_SPI_CS 0 #define CONFIG_ENV_SPI_MAX_HZ 20000000 @@ -108,7 +96,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD -#define CONFIG_SYS_FSL_DDR3 #define CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SYS_SPD_BUS_NUM 0 @@ -162,11 +149,8 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#define CONFIG_BCH - /* NAND flash config */ #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | BR_PS_8 /* Port Size = 8 bit */ \ @@ -203,15 +187,8 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */ #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */ -/* bootcounter in QRIO */ -#define CONFIG_BOOTCOUNT_LIMIT -#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_QRIO_BASE + 0x20) - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ #define CONFIG_MISC_INIT_F #define CONFIG_MISC_INIT_R -#define CONFIG_LAST_STAGE_INIT #define CONFIG_HWCONFIG @@ -239,7 +216,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); * open - index 2 * shorted - index 1 */ -#define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -310,7 +286,6 @@ int get_scl(void); #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* Qman/Bman */ -#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ #define CONFIG_SYS_BMAN_NUM_PORTALS 10 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull @@ -349,19 +324,15 @@ int get_scl(void); #define CONFIG_FMAN_ENET #define CONFIG_PHYLIB_10G -#define CONFIG_PHY_MARVELL /* there is a marvell phy */ #define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_DOS_PARTITION /* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */ #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x11 #define CONFIG_SYS_TBIPA_VALUE 8 -#define CONFIG_PHYLIB /* recommended PHY management */ #define CONFIG_ETHPRIME "FM1@DTSEC5" -#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ /* * Environment @@ -380,11 +351,8 @@ int get_scl(void); /* * additionnal command line configuration. */ -#define CONFIG_CMD_PCI -#define CONFIG_CMD_ERRATA /* we don't need flash support */ -#define CONFIG_SYS_NO_FLASH #undef CONFIG_FLASH_CFI_MTD #undef CONFIG_JFFS2_CMDLINE @@ -411,16 +379,6 @@ int get_scl(void); #define CONFIG_KM_DEF_ENV "km-common=empty\0" #endif -#ifndef MTDIDS_DEFAULT -# define MTDIDS_DEFAULT "nand0=fsl_elbc_nand" -#endif /* MTDIDS_DEFAULT */ - -#ifndef MTDPARTS_DEFAULT -# define MTDPARTS_DEFAULT "mtdparts=" \ - "fsl_elbc_nand:" \ - "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" -#endif /* MTDPARTS_DEFAULT */ - /* architecture specific default bootargs */ #define CONFIG_KM_DEF_BOOT_ARGS_CPU "" @@ -431,7 +389,7 @@ int get_scl(void); "cramfsload ${fdt_addr_r} " \ "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \ "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \ - "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.pbl\0" \ + "u-boot="CONFIG_HOSTNAME "/u-boot.pbl\0" \ "update=" \ "sf probe 0;sf erase 0 +${filesize};" \ "sf write ${load_addr_r} 0 ${filesize};\0" \