X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fkm8360.h;h=c8039e121b2072f9ae63eed0c99d5cb9fd50866b;hb=89ca873e2ddea859526f25f678fa53dda055e90f;hp=f5ac32a332246fe2b7be3d1881cb5facc0b450d5;hpb=326ea986ac150acdc7656d57fca647db80b50158;p=u-boot

diff --git a/include/configs/km8360.h b/include/configs/km8360.h
index f5ac32a332..c8039e121b 100644
--- a/include/configs/km8360.h
+++ b/include/configs/km8360.h
@@ -9,6 +9,8 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#define CONFIG_DISPLAY_BOARDINFO
+
 /* KMBEC FPGA (PRIO) */
 #define CONFIG_SYS_KMBEC_FPGA_BASE	0xE8000000
 #define CONFIG_SYS_KMBEC_FPGA_SIZE	64
@@ -97,7 +99,7 @@
 #define CONFIG_SYS_DDR_CS0_CONFIG (\
 	CSCONFIG_EN | \
 	CSCONFIG_AP | \
-	CSCONFIG_ODT_RD_ONLY_CURRENT | \
+	CSCONFIG_ODT_WR_ONLY_CURRENT | \
 	CSCONFIG_BANK_BIT_3 | \
 	CSCONFIG_ROW_BIT_13 | \
 	CSCONFIG_COL_BIT_10)
@@ -105,7 +107,7 @@
 #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
 					 CSCONFIG_ROW_BIT_13 | \
 					 CSCONFIG_COL_BIT_10 | \
-					 CSCONFIG_ODT_RD_ONLY_CURRENT)
+					 CSCONFIG_ODT_WR_ONLY_CURRENT)
 #endif
 
 #define CONFIG_SYS_DDR_CLK_CNTL (\
@@ -231,7 +233,6 @@
 
 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
 
-
 #ifdef CONFIG_KMCOGE5NE
 /* BFTIC3:  icache cacheable, but dcache-inhibit and guarded */
 #define CONFIG_SYS_IBAT6L (\