X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fkmeter1.h;h=6b5a6feaf7bc1f61fa383539d157e3ac9bee8d80;hb=ed97abed27455b4f9e0dec6274976f5010258ed9;hp=8639ddd96f4b3542280b25ded0d4bd6e0566290a;hpb=264eaa0ea967bac32214b87d60cfc86c8b22cac6;p=u-boot

diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h
index 8639ddd96f..6b5a6feaf7 100644
--- a/include/configs/kmeter1.h
+++ b/include/configs/kmeter1.h
@@ -49,7 +49,7 @@
 	HRCWL_CSB_TO_CLKIN_4X1 | \
 	HRCWL_CORE_TO_CSB_2X1 | \
 	HRCWL_CE_PLL_VCO_DIV_2 | \
-	HRCWL_CE_TO_PLL_1X6 )
+	HRCWL_CE_TO_PLL_1X6)
 
 #define CONFIG_SYS_HRCW_HIGH (\
 	HRCWH_CORE_ENABLE | \
@@ -59,7 +59,7 @@
 	HRCWH_ROM_LOC_LOCAL_16BIT | \
 	HRCWH_BIG_ENDIAN | \
 	HRCWH_LALE_EARLY | \
-	HRCWH_LDP_CLEAR )
+	HRCWH_LDP_CLEAR)
 
 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000007f
 #define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SDRAM_TYPE_DDR2 | \
@@ -72,9 +72,10 @@
 #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN | CSCONFIG_AP | \
 					 CSCONFIG_ROW_BIT_13 | \
 					 CSCONFIG_COL_BIT_10 | \
-					 CSCONFIG_ODT_WR_ACS)
+					 CSCONFIG_ODT_WR_ONLY_CURRENT)
 
-#define	CONFIG_SYS_DDRCDR		0x40000001
+#define	CONFIG_SYS_DDRCDR		(DDRCDR_EN | DDRCDR_Q_DRN)
+					/* 0x40000001 */
 #define CONFIG_SYS_DDR_MODE		0x47860452
 #define CONFIG_SYS_DDR_MODE2		0x8080c000
 
@@ -136,37 +137,38 @@
  * PAXE on the local bus CS3
  */
 #define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_PAXE_BASE
-#define CONFIG_SYS_LBLAWAR3_PRELIM	0x8000001C /* 512MB window size */
+#define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_512MB)
 
 #define CONFIG_SYS_BR3_PRELIM	(CONFIG_SYS_PAXE_BASE | \
-				(1 << BR_PS_SHIFT) | /* 8 bit port size */ \
+				BR_PS_8 | /* 8 bit port size */ \
+				BR_MS_GPCM | /* MSEL = GPCM */ \
 				BR_V)
 #define CONFIG_SYS_OR3_PRELIM	(MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
 				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 				OR_GPCM_SCY_2 | \
-				OR_GPCM_TRLX | OR_GPCM_EAD)
+				OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 
 /*
  * MMU Setup
  */
 
 /* PAXE:  icache cacheable, but dcache-inhibit and guarded */
-#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PAXE_BASE | BATL_PP_RW | \
 				 BATL_MEMCOHERENCE)
 #define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PAXE_BASE | BATU_BL_256M | \
 				 BATU_VS | BATU_VP)
-#define CONFIG_SYS_DBAT5L	(CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
+#define CONFIG_SYS_DBAT5L	(CONFIG_SYS_PAXE_BASE | BATL_PP_RW | \
 				 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
 
 #ifdef CONFIG_PCI
 /* PCI MEM space: cacheable */
-#define CFG_IBAT6L	(CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT6L	(CFG_PCI1_MEM_PHYS | BATL_PP_RW | BATL_MEMCOHERENCE)
 #define CFG_IBAT6U	(CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CFG_DBAT6L	CFG_IBAT6L
 #define CFG_DBAT6U	CFG_IBAT6U
 /* PCI MMIO space: cache-inhibit and guarded */
-#define CFG_IBAT7L	(CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
+#define CFG_IBAT7L	(CFG_PCI1_MMIO_PHYS | BATL_PP_RW | \
 			 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CFG_IBAT7U	(CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CFG_DBAT7L	CFG_IBAT7L