X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fls1021aqds.h;h=c7f503371d674b22c1625f8030b39c8ce9d055fb;hb=dbf38aabd9f4d4fd4d9bd4eeeba88e0e47dcb27c;hp=296ded9f5e9915551de3293212c9dc35c66a725b;hpb=8fc2121a10e92bfd7cb1db50fb110d3ca9acfbda;p=u-boot diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 296ded9f5e..eb444ebd59 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -7,11 +7,12 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include - #define CONFIG_LS102XA -#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_ARMV7_PSCI +#define CONFIG_ARMV7_PSCI_NR_CPUS CONFIG_MAX_CPUS + +#define CONFIG_SYS_FSL_CLK #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -19,6 +20,11 @@ #define CONFIG_SKIP_LOWLEVEL_INIT #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DEEP_SLEEP +#if defined(CONFIG_DEEP_SLEEP) +#define CONFIG_SILENT_CONSOLE +#endif + /* * Size of malloc() pool */ @@ -37,7 +43,7 @@ unsigned long get_board_sys_clk(void); unsigned long get_board_ddr_clk(void); #endif -#ifdef CONFIG_QSPI_BOOT +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_SYS_CLK_FREQ 100000000 #define CONFIG_DDR_CLK_FREQ 100000000 #define CONFIG_QIXIS_I2C_ACCESS @@ -51,7 +57,13 @@ unsigned long get_board_ddr_clk(void); #endif #ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg +#ifdef CONFIG_SD_BOOT_QSPI +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1021aqds/ls102xa_rcw_sd_qspi.cfg +#else +#define CONFIG_SYS_FSL_PBL_RCW \ + board/freescale/ls1021aqds/ls102xa_rcw_sd_ifc.cfg +#endif #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" #define CONFIG_SPL_LIBCOMMON_SUPPORT @@ -64,7 +76,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SPL_DRIVERS_MISC_SUPPORT #define CONFIG_SPL_MMC_SUPPORT #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8 -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400 +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x600 #define CONFIG_SPL_TEXT_BASE 0x10000000 #define CONFIG_SPL_MAX_SIZE 0x1a000 @@ -72,15 +84,19 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SPL_PAD_TO 0x1c000 #define CONFIG_SYS_TEXT_BASE 0x82000000 -#define CONFIG_SYS_SPL_MALLOC_START 0x80200000 +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \ + CONFIG_SYS_MONITOR_LEN) #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 #define CONFIG_SPL_BSS_START_ADDR 0x80100000 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 -#define CONFIG_SYS_MONITOR_LEN 0x80000 +#define CONFIG_SYS_MONITOR_LEN 0xc0000 #endif #ifdef CONFIG_QSPI_BOOT #define CONFIG_SYS_TEXT_BASE 0x40010000 +#endif + +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_SYS_NO_FLASH #endif @@ -118,7 +134,7 @@ unsigned long get_board_ddr_clk(void); #endif #ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0x67f80000 +#define CONFIG_SYS_TEXT_BASE 0x60100000 #endif #define CONFIG_NR_DRAM_BANKS 1 @@ -156,7 +172,7 @@ unsigned long get_board_ddr_clk(void); /* * IFC Definitions */ -#ifndef CONFIG_QSPI_BOOT +#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_FSL_IFC #define CONFIG_SYS_FLASH_BASE 0x60000000 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE @@ -245,7 +261,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) @@ -366,13 +381,13 @@ unsigned long get_board_ddr_clk(void); * Serial Port */ #ifdef CONFIG_LPUART -#define CONFIG_FSL_LPUART #define CONFIG_LPUART_32B_REG #else #define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL +#ifndef CONFIG_DM_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 +#endif #define CONFIG_SYS_NS16550_CLK get_serial_clock() #endif @@ -381,9 +396,11 @@ unsigned long get_board_ddr_clk(void); /* * I2C */ -#define CONFIG_CMD_I2C #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ /* * I2C bus multiplexer @@ -396,40 +413,50 @@ unsigned long get_board_ddr_clk(void); * MMC */ #define CONFIG_MMC -#define CONFIG_CMD_MMC #define CONFIG_FSL_ESDHC #define CONFIG_GENERIC_MMC -#define CONFIG_CMD_FAT #define CONFIG_DOS_PARTITION +/* SPI */ +#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) /* QSPI */ -#ifdef CONFIG_QSPI_BOOT -#define CONFIG_FSL_QSPI #define QSPI0_AMBA_BASE 0x40000000 #define FSL_QSPI_FLASH_SIZE (1 << 24) #define FSL_QSPI_FLASH_NUM 2 -#define CONFIG_CMD_SF -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_SPANSION +/* DSPI */ + +/* DM SPI */ +#if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI) +#define CONFIG_DM_SPI_FLASH +#define CONFIG_SPI_FLASH_DATAFLASH +#endif #endif /* * USB */ -#define CONFIG_HAS_FSL_DR_USB +/* EHCI Support - disbaled by default */ +/*#define CONFIG_HAS_FSL_DR_USB*/ #ifdef CONFIG_HAS_FSL_DR_USB #define CONFIG_USB_EHCI - -#ifdef CONFIG_USB_EHCI -#define CONFIG_CMD_USB -#define CONFIG_USB_STORAGE #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET -#define CONFIG_CMD_EXT2 #endif + +/*XHCI Support - enabled by default*/ +#define CONFIG_HAS_FSL_XHCI_USB + +#ifdef CONFIG_HAS_FSL_XHCI_USB +#define CONFIG_USB_XHCI_FSL +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1 +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 +#endif + +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB) +#define CONFIG_USB_STORAGE #endif /* @@ -444,6 +471,7 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_VGA_AS_SINGLE_DEVICE #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_SYS_CONSOLE_IS_IN_ENV #define CONFIG_FSL_DIU_CH7301 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0 @@ -499,51 +527,61 @@ unsigned long get_board_ddr_clk(void); /* PCIe */ #define CONFIG_PCI /* Enable PCI/PCIE */ -#define CONFIG_PCIE1 /* PCIE controler 1 */ -#define CONFIG_PCIE2 /* PCIE controler 2 */ +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */ #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie" -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_MII -#define CONFIG_CMD_NET +#define CONFIG_SYS_PCI_64BIT -#define CONFIG_CMDLINE_TAG -#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000 +#define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */ +#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000 +#define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */ -#ifdef CONFIG_QSPI_BOOT -#undef CONFIG_CMD_IMLS -#else -#define CONFIG_CMD_IMLS +#define CONFIG_SYS_PCIE_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000 +#define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */ + +#define CONFIG_SYS_PCIE_MEM_BUS 0x08000000 +#define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000 +#define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */ + +#ifdef CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_SCAN_SHOW +#define CONFIG_CMD_PCI #endif +#define CONFIG_CMDLINE_TAG +#define CONFIG_CMDLINE_EDITING + #define CONFIG_ARMV7_NONSEC #define CONFIG_ARMV7_VIRT #define CONFIG_PEN_ADDR_BIG_ENDIAN -#define CONFIG_LS102XA_NS_ACCESS +#define CONFIG_LAYERSCAPE_NS_ACCESS #define CONFIG_SMP_PEN_ADDR 0x01ee0200 #define CONFIG_TIMER_CLK_FREQ 12500000 -#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR #define CONFIG_HWCONFIG -#define HWCONFIG_BUFFER_SIZE 128 +#define HWCONFIG_BUFFER_SIZE 256 -#define CONFIG_BOOTDELAY 3 +#define CONFIG_FSL_DEVICE_DISABLE -#define CONFIG_SYS_QE_FW_ADDR 0x67f40000 + +#define CONFIG_SYS_QE_FW_ADDR 0x600c0000 #ifdef CONFIG_LPUART #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \ - "fdt_high=0xcfffffff\0" \ - "initrd_high=0xcfffffff\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" #else #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \ - "fdt_high=0xcfffffff\0" \ - "initrd_high=0xcfffffff\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0" #endif @@ -551,8 +589,6 @@ unsigned long get_board_ddr_clk(void); * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE \ @@ -560,10 +596,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_CMD_ENV_EXISTS -#define CONFIG_CMD_GREPENV -#define CONFIG_CMD_MEMINFO -#define CONFIG_CMD_MEMTEST #define CONFIG_SYS_MEMTEST_START 0x80000000 #define CONFIG_SYS_MEMTEST_END 0x9fffffff @@ -614,18 +646,15 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ #endif -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP -#define CONFIG_CMD_BOOTZ - #define CONFIG_MISC_INIT_R /* Hash command with SHA acceleration supported in hardware */ +#ifdef CONFIG_FSL_CAAM #define CONFIG_CMD_HASH #define CONFIG_SHA_HW_ACCEL - -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB #endif +#include +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + #endif