X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fls2080a_simu.h;h=f44b9e49c11bd9ffda06d8090eb1de7c6125295f;hb=7514ed33d21318edb5d28ab0f4afc23625fd3530;hp=0dbe95f406967d70fa851fa4d512de86439b0973;hpb=43d3fb5c0609a76409e7859a2a5800670c7b5bd2;p=u-boot

diff --git a/include/configs/ls2080a_simu.h b/include/configs/ls2080a_simu.h
index 0dbe95f406..f44b9e49c1 100644
--- a/include/configs/ls2080a_simu.h
+++ b/include/configs/ls2080a_simu.h
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2014 Freescale Semiconductor
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef __LS2_SIMU_H
@@ -9,15 +8,9 @@
 
 #include "ls2080a_common.h"
 
-#define CONFIG_IDENT_STRING		" LS2080A-SIMU"
-#define CONFIG_BOOTP_VCI_STRING		"U-Boot.LS2080A-SIMU"
-
 #define CONFIG_SYS_CLK_FREQ	100000000
 #define CONFIG_DDR_CLK_FREQ	133333333
 
-#define CONFIG_SYS_MXC_I2C1_SPEED	40000000
-#define CONFIG_SYS_MXC_I2C2_SPEED	40000000
-
 #define CONFIG_DIMM_SLOTS_PER_CTLR		1
 #define CONFIG_CHIP_SELECTS_PER_CTRL		4
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
@@ -31,6 +24,13 @@
 #define CONFIG_SYS_NOR0_CSPR_EXT	(0x0)
 #define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
 
+#ifdef CONFIG_MTD_NOR_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#endif
+
 /*
  * NOR Flash Timing Params
  */
@@ -56,7 +56,7 @@
 #define CONFIG_SYS_NOR_FTIM3	0x04000000
 #define CONFIG_SYS_IFC_CCR	0x01000000
 
-#ifndef CONFIG_SYS_NO_FLASH
+#ifdef CONFIG_MTD_NOR_FLASH
 #define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
 
 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
@@ -72,7 +72,6 @@
 #define CONFIG_SYS_NAND_MAX_ECCPOS	256
 #define CONFIG_SYS_NAND_MAX_OOBFREE	2
 
-
 #define CONFIG_SYS_NAND_CSPR_EXT	(0x0)
 #define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
@@ -107,7 +106,6 @@
 #define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_CMD_NAND
 
 #define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
 
@@ -130,14 +128,8 @@
 #define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NAND_FTIM3
 
 /*  MMC  */
-#define CONFIG_MMC
 #ifdef CONFIG_MMC
-#define CONFIG_CMD_MMC
-#define CONFIG_FSL_ESDHC
 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
-#define CONFIG_GENERIC_MMC
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
 #endif
 
 /* Debug Server firmware */
@@ -145,9 +137,6 @@
 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR	0x580C00000ULL
 
 /* MC firmware */
-#define CONFIG_SYS_LS_MC_FW_IN_NOR
-#define CONFIG_SYS_LS_MC_FW_ADDR	0x580200000ULL
-
 #define CONFIG_SYS_LS_MC_DPL_IN_NOR
 #define CONFIG_SYS_LS_MC_DPL_ADDR	0x5806C0000ULL
 
@@ -157,7 +146,6 @@
 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 200000
 
 /* Store environment at top of flash */
-#define CONFIG_ENV_IS_NOWHERE		1
 #define CONFIG_ENV_SIZE			0x1000
 
 #endif /* __LS2_SIMU_H */