X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fluan.h;h=3b4761bd08719919657851195e4067026446446a;hb=810c44274980d8bb9fa0d81d091a374adbae8309;hp=ccd9397df4ee01080bcec1340a315e5e07e73a37;hpb=bf56080769f13025daaeb80d967eea19e7f78d60;p=u-boot diff --git a/include/configs/luan.h b/include/configs/luan.h index ccd9397df4..3b4761bd08 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -37,6 +37,8 @@ #define CONFIG_440 1 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ +#define CONFIG_SYS_TEXT_BASE 0xFFFB0000 + /* * Include common defines/options for all AMCC eval boards */ @@ -58,8 +60,6 @@ #define CONFIG_SYS_ISRAM_BASE 0xf8000000 /* internal 8k SRAM (L2 cache) */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xf0000000 /* internal peripherals */ - #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */ @@ -80,16 +80,15 @@ * Initial RAM & stack pointer (placed in SDRAM) *----------------------------------------------------------------------*/ #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE -#define CONFIG_SYS_INIT_RAM_END (8 << 10) -#define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE (8 << 10) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* external 11.059MHz clk */ -#undef CONFIG_UART1_CONSOLE /* define if you want console on UART1 */ /*----------------------------------------------------------------------- * Environment