X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fmanroland%2Fmpc5200-common.h;h=736bebbe1cb9156cc22428504606082a07472036;hb=5b8e76c35ec312a3f73126bd1a2d2c0965b98a9f;hp=7be135478ff5034ac268faf41605ae016dacbbba;hpb=d48455ad8cefd25d7b49f68fd16d0e9fd551732a;p=u-boot

diff --git a/include/configs/manroland/mpc5200-common.h b/include/configs/manroland/mpc5200-common.h
index 7be135478f..736bebbe1c 100644
--- a/include/configs/manroland/mpc5200-common.h
+++ b/include/configs/manroland/mpc5200-common.h
@@ -2,23 +2,7 @@
  * (C) Copyright 2009
  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef __MANROLAND_MPC52XX__COMMON_H
@@ -28,12 +12,12 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU		*/
-#define CONFIG_MPC5200		1	/* (more precisely an MPC5200 CPU)	*/
+#define CONFIG_MPC5200		1	/* MPC5200 CPU */
 
-#define CONFIG_SYS_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz	*/
+/* ... running at 33.000000MHz	*/
+#define CONFIG_SYS_MPC5XXX_CLKIN	33000000
 
-#define CONFIG_HIGH_BATS	1	/* High BATs supported 			*/
+#define CONFIG_HIGH_BATS	1	/* High BATs supported		*/
 
 /*
  * Serial console configuration
@@ -51,36 +35,6 @@
  */
 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK		/* define for 133MHz speed */
 
-/*
- * I2C configuration
- */
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #1 or #2 */
-
-#define CONFIG_SYS_I2C_SPEED		100000 /* 100 kHz */
-#define CONFIG_SYS_I2C_SLAVE		0x7F
-
-/*
- * EEPROM configuration
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x58
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	4
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10
-
-/*
- * RTC configuration
- */
-#define CONFIG_RTC_PCF8563
-#define CONFIG_SYS_I2C_RTC_ADDR		0x51
-
-/* I2C SYSMON (LM75) */
-#define CONFIG_DTT_LM81			1	/* ON Semi's LM75	*/
-#define CONFIG_DTT_SENSORS		{0}	/* Sensor addresses	*/
-#define CONFIG_SYS_DTT_MAX_TEMP		70
-#define CONFIG_SYS_DTT_LOW_TEMP		-30
-#define CONFIG_SYS_DTT_HYSTERESIS		3
-
 /*
  * Flash configuration
  */
@@ -88,7 +42,7 @@
 
 #define CONFIG_SYS_FLASH_SIZE		0x00800000 /* 8 MByte */
 
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_TEXT_BASE+0x40000) /* second sector */
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_TEXT_BASE+0x40000) /* second sector */
 #define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks
 					   (= chip selects) */
 #define CONFIG_SYS_FLASH_ERASE_TOUT	240000	/* Flash Erase Timeout [ms]*/
@@ -113,9 +67,8 @@
 #define CONFIG_SYS_MBAR		0xF0000000
 #define CONFIG_SYS_DEFAULT_MBAR	0x80000000
 
-#define CONFIG_SYS_GBL_DATA_SIZE	128
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END -\
-					 CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE -\
+					 GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
@@ -135,9 +88,9 @@
 #define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
 #ifdef CONFIG_POST
 /* preserve space for the post_word at end of on-chip SRAM */
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_POST_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
 #else
-#define CONFIG_SYS_INIT_RAM_END	MPC5XXX_SRAM_SIZE
+#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
 #endif
 
 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
@@ -160,11 +113,9 @@
 /*use  Hardware WDT */
 #define CONFIG_HW_WATCHDOG
 
-#define CONFIG_SYS_HZ			1000	/* decrementer freq: 1 ms ticks */
-
-#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs		*/
+#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs	*/
 #if defined(CONFIG_CMD_KGDB)
-#  define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value*/
+#  define CONFIG_SYS_CACHELINE_SHIFT	5 /* log base 2 of the above value */
 #endif
 
 /*
@@ -189,9 +140,6 @@
  *-----------------------------------------------------------------------
  */
 
-#undef  CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/
-
-#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
 #undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
 
 #define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus	*/