X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fmecp5200.h;h=b270429dd821875253f44e4329410f171421f2f0;hb=b1cdd8baa14f518288ceddb391d6587c1ecb3174;hp=a9ea5397660288f2ee47803e300b9cef2030db2c;hpb=0defddc851edfc34bcf3c3379fe74b11dc01a493;p=u-boot

diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h
index a9ea539766..b270429dd8 100644
--- a/include/configs/mecp5200.h
+++ b/include/configs/mecp5200.h
@@ -23,8 +23,7 @@
  * (easy to change)
  */
 
-#define CONFIG_MPC5200		1	/* This is an MPC5xxx CPU */
-#define CONFIG_MPC5xxx		1	/* This is an MPC5xxx CPU */
+#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
 #define CONFIG_ICECUBE		1	/* ... on IceCube board */
 #define CONFIG_MECP5200		1	/* ... on MECP5200  board */
 #define CONFIG_MPC5200_DDR      1       /* ... use DDR RAM      */
@@ -249,8 +248,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000		/* decrementer freq: 1 ms ticks */
-
 #define CONFIG_SYS_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
 
 #define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */