X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fmx31pdk.h;h=4253c3e2bcf037188dcedad647b42b9dab9dffdf;hb=18b6ddfdf1a1b8cc2362af9e0d0c88087c0d6b0b;hp=a4862c6fc5a204b325a0da6c7ef2e32dd634d63c;hpb=a48ecc969f8d2d0fe9167962e9b8b4cca52de10b;p=u-boot

diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index a4862c6fc5..4253c3e2bc 100644
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -30,48 +30,56 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
+#include <asm/arch/imx-regs.h>
+
 /* High Level Configuration Options */
-#define CONFIG_ARM1136		1	/* This is an arm1136 CPU core */
-#define CONFIG_MX31		1	/* in a mx31 */
+#define CONFIG_ARM1136			/* This is an arm1136 CPU core */
+#define CONFIG_MX31			/* in a mx31 */
 #define CONFIG_MX31_HCLK_FREQ	26000000
 #define CONFIG_MX31_CLK32	32768
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
-#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS	1
-#define CONFIG_INITRD_TAG		1
+#define CONFIG_CMDLINE_TAG			/* enable passing of ATAGs */
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_MACH_TYPE	MACH_TYPE_MX31_3DS
 
 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 #define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
 #endif
 
 /*
  * Size of malloc() pool
  */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + 128 * 1024)
-/* Bytes reserved for initial data */
-#define CONFIG_SYS_GBL_DATA_SIZE	128
+#define CONFIG_SYS_MALLOC_LEN		(2*CONFIG_ENV_SIZE + 2 * 128 * 1024)
 
 /*
  * Hardware drivers
  */
 
-#define CONFIG_MXC_UART		1
-#define CONFIG_SYS_MX31_UART1	1
+#define CONFIG_MXC_UART
+#define CONFIG_SYS_MX31_UART1
+#define CONFIG_HW_WATCHDOG
+#define CONFIG_MXC_GPIO
 
-#define CONFIG_HARD_SPI		1
-#define CONFIG_MXC_SPI		1
+#define CONFIG_HARD_SPI
+#define CONFIG_MXC_SPI
 #define CONFIG_DEFAULT_SPI_BUS	1
-#define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_2 | SPI_CS_HIGH)
-
-#define CONFIG_RTC_MC13783	1
-
-/* MC13783 connected to CSPI2 and SS2 */
-#define CONFIG_MC13783_SPI_BUS	1
-#define CONFIG_MC13783_SPI_CS	2
+#define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
+
+/* PMIC Controller */
+#define CONFIG_PMIC
+#define CONFIG_PMIC_SPI
+#define CONFIG_PMIC_FSL
+#define CONFIG_FSL_PMIC_BUS	1
+#define CONFIG_FSL_PMIC_CS	2
+#define CONFIG_FSL_PMIC_CLK	1000000
+#define CONFIG_FSL_PMIC_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
+#define CONFIG_FSL_PMIC_BITLEN	32
+#define CONFIG_RTC_MC13XXX
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
@@ -87,8 +95,10 @@
 
 #define CONFIG_CMD_MII
 #define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_SPI
 #define CONFIG_CMD_DATE
+#define CONFIG_CMD_NAND
 
 /*
  * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require
@@ -96,6 +106,8 @@
  */
 #undef CONFIG_CMD_IMLS
 
+#define CONFIG_BOARD_LATE_INIT
+
 #define CONFIG_BOOTDELAY	3
 
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
@@ -104,17 +116,20 @@
 		"ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"	\
 	"bootcmd=run bootcmd_net\0"					\
 	"bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; "	\
-		"tftpboot 0x81000000 uImage-mx31; bootm\0"
+		"tftpboot 0x81000000 uImage-mx31; bootm\0"		\
+	"prg_uboot=tftpboot 0x81000000 u-boot-nand.bin; "		\
+		"nand erase 0x0 0x40000; "				\
+		"nand write 0x81000000 0x0 0x40000\0"
 
-#define CONFIG_DRIVER_SMC911X		1
-#define CONFIG_DRIVER_SMC911X_BASE	0xB6000000
-#define CONFIG_DRIVER_SMC911X_32_BIT	1
+#define CONFIG_SMC911X
+#define CONFIG_SMC911X_BASE	0xB6000000
+#define CONFIG_SMC911X_32_BIT
 
 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP	/* undef to save memory */
-#define CONFIG_SYS_PROMPT	"uboot> "
+#define CONFIG_SYS_PROMPT	"MX31PDK U-Boot > "
 #define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
 /* Print Buffer Size */
 #define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
@@ -133,7 +148,7 @@
 
 #define CONFIG_SYS_HZ			1000
 
-#define CONFIG_CMDLINE_EDITING	1
+#define CONFIG_CMDLINE_EDITING
 
 /*-----------------------------------------------------------------------
  * Stack sizes
@@ -148,16 +163,36 @@
 #define CONFIG_NR_DRAM_BANKS	1
 #define PHYS_SDRAM_1		CSD0_BASE
 #define PHYS_SDRAM_1_SIZE	(128 * 1024 * 1024)
+#define CONFIG_BOARD_EARLY_INIT_F
+
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define CONFIG_SYS_INIT_RAM_ADDR	IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE	IRAM_SIZE
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+						GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + \
+						CONFIG_SYS_GBL_DATA_OFFSET)
 
 /*-----------------------------------------------------------------------
  * FLASH and environment organization
  */
 /* No NOR flash present */
-#define CONFIG_SYS_NO_FLASH	1
+#define CONFIG_SYS_NO_FLASH
 
-#define CONFIG_ENV_IS_NOWHERE	1
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_OFFSET		0x40000
+#define CONFIG_ENV_OFFSET_REDUND	0x60000
+#define CONFIG_ENV_SIZE			(128 * 1024)
 
-#define CONFIG_ENV_SIZE		(128 * 1024)
+/*
+ * NAND driver
+ */
+#define CONFIG_NAND_MXC
+#define CONFIG_MXC_NAND_REGS_BASE      NFC_BASE_ADDR
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_SYS_NAND_BASE           NFC_BASE_ADDR
+#define CONFIG_MXC_NAND_HWECC
+#define CONFIG_SYS_NAND_LARGEPAGE
 
 /* NAND configuration for the NAND_SPL */