X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fmx31pdk.h;h=82ea4fa92ebea1278f9b2268353f12f961dce189;hb=ca85eb8c4271509aaac1ccb26ae3eb1a7827b4e6;hp=3b90a01623933b9995d229ebdb6667f60e310e36;hpb=1032d97496f6d534bf0030a5779ff1cb38cc9ebf;p=u-boot diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h index 3b90a01623..82ea4fa92e 100644 --- a/include/configs/mx31pdk.h +++ b/include/configs/mx31pdk.h @@ -30,22 +30,32 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include +#include /* High Level Configuration Options */ -#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ -#define CONFIG_MX31 1 /* in a mx31 */ -#define CONFIG_MX31_HCLK_FREQ 26000000 -#define CONFIG_MX31_CLK32 32768 +#define CONFIG_ARM1136 /* This is an arm1136 CPU core */ +#define CONFIG_MX31 /* in a mx31 */ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG -#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CONFIG_MACH_TYPE MACH_TYPE_MX31_3DS + +#define CONFIG_SPL +#define CONFIG_SPL_TARGET "u-boot-with-spl.bin" +#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds" +#define CONFIG_SPL_MAX_SIZE 2048 +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT + +#define CONFIG_SPL_TEXT_BASE 0x87dc0000 +#define CONFIG_SYS_TEXT_BASE 0x87e00000 + +#ifndef CONFIG_SPL_BUILD #define CONFIG_SKIP_LOWLEVEL_INIT #endif @@ -53,32 +63,35 @@ * Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (2*CONFIG_ENV_SIZE + 2 * 128 * 1024) -/* Bytes reserved for initial data */ /* * Hardware drivers */ -#define CONFIG_MXC_UART 1 -#define CONFIG_SYS_MX31_UART1 1 +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONFIG_MXC_GPIO -#define CONFIG_HARD_SPI 1 -#define CONFIG_MXC_SPI 1 +#define CONFIG_HARD_SPI +#define CONFIG_MXC_SPI #define CONFIG_DEFAULT_SPI_BUS 1 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) -#define CONFIG_FSL_PMIC +/* PMIC Controller */ +#define CONFIG_POWER +#define CONFIG_POWER_SPI +#define CONFIG_POWER_FSL #define CONFIG_FSL_PMIC_BUS 1 #define CONFIG_FSL_PMIC_CS 2 #define CONFIG_FSL_PMIC_CLK 1000000 #define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) -#define CONFIG_RTC_MC13783 1 +#define CONFIG_FSL_PMIC_BITLEN 32 +#define CONFIG_RTC_MC13XXX /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 #define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} /*********************************************************** * Command definition @@ -88,9 +101,11 @@ #define CONFIG_CMD_MII #define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP #define CONFIG_CMD_SPI #define CONFIG_CMD_DATE #define CONFIG_CMD_NAND +#define CONFIG_CMD_BOOTZ /* * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require @@ -98,7 +113,9 @@ */ #undef CONFIG_CMD_IMLS -#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOARD_LATE_INIT + +#define CONFIG_BOOTDELAY 1 #define CONFIG_EXTRA_ENV_SETTINGS \ "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ @@ -107,20 +124,19 @@ "bootcmd=run bootcmd_net\0" \ "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; " \ "tftpboot 0x81000000 uImage-mx31; bootm\0" \ - "prg_uboot=tftpboot 0x81000000 u-boot-nand.bin; " \ + "prg_uboot=tftpboot 0x81000000 u-boot-with-spl.bin; " \ "nand erase 0x0 0x40000; " \ "nand write 0x81000000 0x0 0x40000\0" -#define CONFIG_NET_MULTI -#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X #define CONFIG_SMC911X_BASE 0xB6000000 -#define CONFIG_SMC911X_32_BIT 1 +#define CONFIG_SMC911X_32_BIT /* * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "uboot> " +#define CONFIG_SYS_PROMPT "MX31PDK U-Boot > " #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ @@ -132,21 +148,14 @@ /* memtest works on */ #define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END 0x10000 +#define CONFIG_SYS_MEMTEST_END 0x80010000 /* default load address */ #define CONFIG_SYS_LOAD_ADDR 0x81000000 #define CONFIG_SYS_HZ 1000 -#define CONFIG_CMDLINE_EDITING 1 - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ +#define CONFIG_CMDLINE_EDITING /*----------------------------------------------------------------------- * Physical Memory Map @@ -154,14 +163,23 @@ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 CSD0_BASE #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) +#define CONFIG_BOARD_EARLY_INIT_F + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE) /*----------------------------------------------------------------------- * FLASH and environment organization */ /* No NOR flash present */ -#define CONFIG_SYS_NO_FLASH 1 +#define CONFIG_SYS_NO_FLASH -#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_OFFSET 0x40000 #define CONFIG_ENV_OFFSET_REDUND 0x60000 #define CONFIG_ENV_SIZE (128 * 1024) @@ -179,10 +197,10 @@ /* NAND configuration for the NAND_SPL */ /* Start copying real U-boot from the second page */ -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x3f800 /* Load U-Boot to this address */ -#define CONFIG_SYS_NAND_U_BOOT_DST 0x87f00000 +#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 @@ -194,11 +212,11 @@ /* Configuration of lowlevel_init.S (clocks and SDRAM) */ #define CCM_CCMR_SETUP 0x074B0BF5 -#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \ - PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | \ - PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | \ - PDR0_MCU_PODF(0)) -#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ +#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \ + PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \ + PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \ + PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)) +#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \ PLL_MFN(12)) #define ESDMISC_MDDR_SETUP 0x00000004