X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fmx53evk.h;h=3bfba35afce44345dec3ec5cfc2cf5b0a1c895ea;hb=de42975141215e7d02e0ab696b3138959bf2042c;hp=11d1278349a5dd4114588aff8411f3b456587b94;hpb=2be296538e2e9d2893dc495b3fc8f9f6acb1454c;p=u-boot diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h index 11d1278349..3bfba35afc 100644 --- a/include/configs/mx53evk.h +++ b/include/configs/mx53evk.h @@ -1,9 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2010 Freescale Semiconductor, Inc. * * Configuration settings for the MX53-EVK Freescale board. - * - * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -23,8 +22,6 @@ /* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) -#define CONFIG_MXC_GPIO - #define CONFIG_MXC_UART #define CONFIG_MXC_UART_BASE UART1_BASE @@ -44,7 +41,6 @@ #define CONFIG_RTC_MC13XXX /* MMC Configs */ -#define CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_ESDHC_NUM 2 @@ -57,14 +53,12 @@ /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_CONS_INDEX 1 /* Command definition */ #define CONFIG_ETHPRIME "FEC0" #define CONFIG_LOADADDR 0x70800000 /* loadaddr env var */ -#define CONFIG_SYS_TEXT_BASE 0x77800000 #define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ @@ -106,22 +100,12 @@ #define CONFIG_ARP_TIMEOUT 200UL /* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ - -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_MEMTEST_START 0x70000000 #define CONFIG_SYS_MEMTEST_END 0x70010000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR -#define CONFIG_CMDLINE_EDITING - /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 CSD0_BASE_ADDR