X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fomap2420h4.h;h=1abf2590ef4b40d8fbe415eb93988712522dd55f;hb=e5f5c4a977c411c0cd3899a4f9487eea77a0e150;hp=92df0b4fdc8c93ff81cec8af5ffd8ae064ccf6c2;hpb=6c869637fef31e66380f0ea1d49690a2e26ec0d7;p=u-boot diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h index 92df0b4fdc..1abf2590ef 100644 --- a/include/configs/omap2420h4.h +++ b/include/configs/omap2420h4.h @@ -38,6 +38,8 @@ /*#define CONFIG_APTIX 1 #* define if on APTIX test chip */ /*#define CONFIG_VIRTIO 1 #* Using Virtio simulator */ +#define CONFIG_STANDALONE_LOAD_ADDR 0x80300000 + /* Clock config to target*/ #define PRCM_CONFIG_II 1 /* #define PRCM_CONFIG_III 1 */ @@ -59,7 +61,6 @@ /* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */ #define CONFIG_SYS_CLK_FREQ V_SCLK -#undef CONFIG_USE_IRQ /* no support for IRQs */ #define CONFIG_MISC_INIT_R #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ @@ -72,7 +73,6 @@ */ #define CONFIG_ENV_SIZE SZ_128K /* Total Size of Environment Sector */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ /* * Hardware drivers @@ -81,7 +81,7 @@ /* * SMC91c96 Etherent */ -#define CONFIG_DRIVER_LAN91C96 +#define CONFIG_LAN91C96 #define CONFIG_LAN91C96_BASE (H4_CS1_BASE+0x300) #define CONFIG_LAN91C96_EXT_PHY @@ -117,8 +117,6 @@ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1 #define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} - /* * Command line configuration. @@ -135,7 +133,7 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_JFFS2 - #undef CONFIG_CMD_AUTOSCRIPT + #undef CONFIG_CMD_SOURCE #endif @@ -147,42 +145,6 @@ #define CONFIG_BOOTP_HOSTNAME #define CONFIG_BOOTP_BOOTPATH - -/* - * Board NAND Info. - */ -#define CONFIG_NAND_LEGACY -#define CONFIG_SYS_NAND_ADDR 0x04000000 /* physical address to access nand at CS0*/ - -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ -#define SECTORSIZE 512 - -#define ADDR_COLUMN 1 -#define ADDR_PAGE 2 -#define ADDR_COLUMN_PAGE 3 - -#define NAND_ChipID_UNKNOWN 0x00 -#define NAND_MAX_FLOORS 1 - -#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0) -#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0) -#define WRITE_NAND(d, adr) do {*(volatile u16 *)0x6800A084 = d;} while(0) -#define READ_NAND(adr) (*(volatile u16 *)0x6800A084) -#define NAND_WAIT_READY(nand) udelay(10) - -#define NAND_NO_RB 1 - -#define CONFIG_SYS_NAND_WP -#define NAND_WP_OFF() do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0) -#define NAND_WP_ON() do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0) - -#define NAND_CTL_CLRALE(nandptr) -#define NAND_CTL_SETALE(nandptr) -#define NAND_CTL_CLRCLE(nandptr) -#define NAND_CTL_SETCLE(nandptr) -#define NAND_DISABLE_CE(nand) -#define NAND_ENABLE_CE(nand) - #define CONFIG_BOOTDELAY 3 #ifdef NFS_BOOT_DEFAULTS @@ -199,14 +161,12 @@ /* * Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ #ifdef CONFIG_APTIX -#define V_PROMPT "OMAP2420 Aptix # " +# define CONFIG_SYS_PROMPT "OMAP2420 Aptix # " #else -#define V_PROMPT "OMAP242x H4 # " +# define CONFIG_SYS_PROMPT "OMAP242x H4 # " #endif - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT V_PROMPT #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) @@ -216,33 +176,20 @@ #define CONFIG_SYS_MEMTEST_START (OMAP2420_SDRC_CS0) /* memtest works on */ #define CONFIG_SYS_MEMTEST_END (OMAP2420_SDRC_CS0+SZ_31M) -#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CONFIG_SYS_LOAD_ADDR (OMAP2420_SDRC_CS0) /* default load address */ /* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by * 32KHz clk, or from external sig. This rate is divided by a local divisor. */ #ifdef CONFIG_APTIX -#define V_PVT 3 +#define V_PTV 3 #else -#define V_PVT 7 /* use with 12MHz/128 */ +#define V_PTV 7 /* use with 12MHz/128 */ #endif -#define CONFIG_SYS_TIMERBASE OMAP2420_GPT2 -#define CONFIG_SYS_PVT V_PVT /* 2^(pvt+1) */ -#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT)) - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE SZ_128K /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ -#endif +#define CONFIG_SYS_TIMERBASE OMAP2420_GPT2 +#define CONFIG_SYS_PTV V_PTV /* 2^(PTV+1) */ +#define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) /*----------------------------------------------------------------------- * Physical Memory Map @@ -258,6 +205,7 @@ #define PHYS_FLASH_2 (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */ #define PHYS_FLASH_SIZE_2 SZ_32M +#define PHYS_SRAM 0x4020F800 /*----------------------------------------------------------------------- * FLASH and environment organization */ @@ -296,7 +244,7 @@ * JFFS2 partitions */ /* No command line, one static partition, whole device */ -#undef CONFIG_JFFS2_CMDLINE +#undef CONFIG_CMD_MTDPARTS #define CONFIG_JFFS2_DEV "nor1" #define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF #define CONFIG_JFFS2_PART_OFFSET 0x00000000 @@ -304,9 +252,12 @@ /* mtdparts command line support */ /* Note: fake mtd_id used, no linux mtd map file */ /* -#define CONFIG_JFFS2_CMDLINE +#define CONFIG_CMD_MTDPARTS #define MTDIDS_DEFAULT "nor1=omap2420-1" #define MTDPARTS_DEFAULT "mtdparts=omap2420-1:-(jffs2)" */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM + #endif /* __CONFIG_H */