X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fomap3_overo.h;h=2f3743cccee5ab5baa3659c6d895005613211b31;hb=2672d5db1d89e94b78c3475d46e16fa23a9d54d8;hp=154554d49a7cfc719ea515247bd70237af7dd149;hpb=54737ba17a8444175fa94d758b83f120bbea3351;p=u-boot diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 154554d49a..2f3743ccce 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -19,16 +19,16 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include /* * High Level Configuration Options */ -#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3430 1 /* which is in a 3430 */ -#define CONFIG_OMAP3_OVERO 1 /* working with overo */ +#define CONFIG_OMAP3_OVERO 1 /* working with overo */ + +#define CONFIG_SDRC /* The chip has SDRC controller */ #include /* get chip and board defs */ #include @@ -51,14 +51,14 @@ #define CONFIG_INITRD_TAG 1 #define CONFIG_REVISION_TAG 1 +#define CONFIG_OF_LIBFDT 1 + /* * Size of malloc() pool */ -#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ - /* initial data */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) /* * Hardware drivers @@ -86,13 +86,18 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 115200} +#define CONFIG_GENERIC_MMC 1 #define CONFIG_MMC 1 -#define CONFIG_OMAP3_MMC 1 +#define CONFIG_OMAP_HSMMC 1 #define CONFIG_DOS_PARTITION 1 +/* DDR - I use Micron DDR */ +#define CONFIG_OMAP3_MICRON_DDR 1 + /* commands to include */ #include +#define CONFIG_CMD_CACHE #define CONFIG_CMD_EXT2 /* EXT2 Support */ #define CONFIG_CMD_FAT /* FAT support */ #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ @@ -105,8 +110,8 @@ #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ #undef CONFIG_CMD_IMI /* iminfo */ #undef CONFIG_CMD_IMLS /* List all found images */ -#undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ #undef CONFIG_CMD_NFS /* NFS support */ +#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ #define CONFIG_SYS_NO_FLASH #define CONFIG_HARD_I2C 1 @@ -114,6 +119,7 @@ #define CONFIG_SYS_I2C_SLAVE 1 #define CONFIG_SYS_I2C_BUS 0 #define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_I2C_MULTI_BUS 1 #define CONFIG_DRIVER_OMAP34XX_I2C 1 /* @@ -125,6 +131,7 @@ /* * Board NAND Info. */ +#define CONFIG_SYS_NAND_QUIET_TEST 1 #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ @@ -135,8 +142,6 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ - #define CONFIG_JFFS2_NAND /* nand device jffs2 lives on */ #define CONFIG_JFFS2_DEV "nand0" @@ -151,20 +156,33 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "console=ttyS2,115200n8\0" \ - "videomode=1024x768@60,vxres=1024,vyres=768\0" \ - "videospec=omapfb:vram:2M,vram:4M\0" \ + "mpurate=500\0" \ + "vram=12M\0" \ + "dvimode=1024x768MR-16@60\0" \ + "defaultdisplay=dvi\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "nandroot=/dev/mtdblock4 rw\0" \ + "nandrootfstype=jffs2\0" \ "mmcargs=setenv bootargs console=${console} " \ - "video=${videospec},mode:${videomode} " \ - "root=/dev/mmcblk0p2 rw " \ - "rootfstype=ext3 rootwait\0" \ + "mpurate=${mpurate} " \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ "nandargs=setenv bootargs console=${console} " \ - "video=${videospec},mode:${videomode} " \ - "root=/dev/mtdblock4 rw " \ - "rootfstype=jffs2\0" \ - "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "mpurate=${mpurate} " \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source ${loadaddr}\0" \ - "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ @@ -174,7 +192,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc init; then " \ + "if mmc rescan ${mmcdev}; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ @@ -189,13 +207,11 @@ /* * Miscellaneous configurable options */ -#define V_PROMPT "Overo # " - #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_PROMPT V_PROMPT -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PROMPT "Overo # " +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) @@ -224,10 +240,10 @@ * * The stack sizes are set up in start.S using the settings below */ -#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ #ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ +#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ #endif /*----------------------------------------------------------------------- @@ -235,7 +251,7 @@ */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /* SDRAM Bank Allocation method */ @@ -251,12 +267,11 @@ #define PISMO1_NAND_SIZE GPMC_SIZE_128M #define PISMO1_ONEN_SIZE GPMC_SIZE_128M -#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ - /* one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ -#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ -#define CONFIG_SYS_FLASH_BASE boot_flash_base +#if defined(CONFIG_CMD_NAND) +#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#endif /* Monitor at start of flash */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE @@ -266,32 +281,27 @@ #define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */ #define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */ -#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec -#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET -/*----------------------------------------------------------------------- - * CFI FLASH driver setup +#if defined(CONFIG_CMD_NET) +/*---------------------------------------------------------------------------- + * SMSC9211 Ethernet from SMSC9118 family + *---------------------------------------------------------------------------- */ -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) - -/* Flash banks JFFS2 should use */ -#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ - CONFIG_SYS_MAX_NAND_DEVICE) -#define CONFIG_SYS_JFFS2_MEM_NAND -/* use flash_info[2] */ -#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 - -#ifndef __ASSEMBLY__ -extern struct gpmc *gpmc_cfg; -extern unsigned int boot_flash_base; -extern volatile unsigned int boot_flash_env_addr; -extern unsigned int boot_flash_off; -extern unsigned int boot_flash_sec; -extern unsigned int boot_flash_type; -#endif + +#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X_32_BIT +#define CONFIG_SMC911X_BASE 0x2C000000 + +#endif /* (CONFIG_CMD_NET) */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) #endif /* __CONFIG_H */