X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fomap3_overo.h;h=c72fb9d8efd1a3a6548626796b59a75e80455268;hb=5bb3505fa867ded03cbee83f7722ab5182930637;hp=1a9192135e6f40f944bceb16ea05a76f1c2f36a0;hpb=2f3b6ef2fe4609c90976ba6aeffd836c6ccb2703;p=u-boot diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 1a9192135e..626cf7afd5 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -13,52 +13,50 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * Foundation, Inc. */ #ifndef __CONFIG_H #define __CONFIG_H -#include /* * High Level Configuration Options */ -#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP34XX 1 /* which is a 34XX */ -#define CONFIG_OMAP3430 1 /* which is in a 3430 */ -#define CONFIG_OMAP3_OVERO 1 /* working with overo */ +#define CONFIG_OMAP /* in a TI OMAP core */ +#define CONFIG_OMAP34XX /* which is a 34XX */ +#define CONFIG_OMAP3_OVERO /* working with overo */ +#define CONFIG_OMAP_GPIO -#include /* get chip and board defs */ +#define CONFIG_SDRC /* The chip has SDRC controller */ + +#include /* get chip and board defs */ #include /* * Display CPU and Board information */ -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK >> 1) -#undef CONFIG_USE_IRQ /* no support for IRQs */ #define CONFIG_MISC_INIT_R -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_OF_LIBFDT /* * Size of malloc() pool */ -#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ - /* initial data */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) /* * Hardware drivers @@ -67,7 +65,7 @@ /* * NS16550 Configuration */ -#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL @@ -86,13 +84,15 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ 115200} -#define CONFIG_MMC 1 -#define CONFIG_OMAP3_MMC 1 -#define CONFIG_DOS_PARTITION 1 +#define CONFIG_GENERIC_MMC +#define CONFIG_MMC +#define CONFIG_OMAP_HSMMC +#define CONFIG_DOS_PARTITION /* commands to include */ #include +#define CONFIG_CMD_CACHE #define CONFIG_CMD_EXT2 /* EXT2 Support */ #define CONFIG_CMD_FAT /* FAT support */ #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ @@ -109,34 +109,32 @@ #define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */ #define CONFIG_SYS_NO_FLASH -#define CONFIG_HARD_I2C 1 +#define CONFIG_HARD_I2C #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_SYS_I2C_BUS 0 -#define CONFIG_SYS_I2C_BUS_SELECT 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_DRIVER_OMAP34XX_I2C /* * TWL4030 */ -#define CONFIG_TWL4030_POWER 1 -#define CONFIG_TWL4030_LED 1 +#define CONFIG_TWL4030_POWER +#define CONFIG_TWL4030_LED /* * Board NAND Info. */ +#define CONFIG_SYS_NAND_QUIET_TEST #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ /* to access nand */ #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ /* to access nand */ /* at CS0 */ -#define GPMC_NAND_ECC_LP_x16_LAYOUT 1 +#define GPMC_NAND_ECC_LP_x16_LAYOUT #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ -#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ - #define CONFIG_JFFS2_NAND /* nand device jffs2 lives on */ #define CONFIG_JFFS2_DEV "nand0" @@ -150,21 +148,37 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ - "console=ttyS2,115200n8\0" \ - "videomode=1024x768@60,vxres=1024,vyres=768\0" \ - "videospec=omapfb:vram:2M,vram:4M\0" \ + "console=ttyO2,115200n8\0" \ + "mpurate=500\0" \ + "optargs=\0" \ + "vram=12M\0" \ + "dvimode=1024x768MR-16@60\0" \ + "defaultdisplay=dvi\0" \ + "mmcdev=0\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "nandroot=ubi0:rootfs ubi.mtd=4\0" \ + "nandrootfstype=ubifs\0" \ "mmcargs=setenv bootargs console=${console} " \ - "video=${videospec},mode:${videomode} " \ - "root=/dev/mmcblk0p2 rw " \ - "rootfstype=ext3 rootwait\0" \ + "${optargs} " \ + "mpurate=${mpurate} " \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ "nandargs=setenv bootargs console=${console} " \ - "video=${videospec},mode:${videomode} " \ - "root=/dev/mtdblock4 rw " \ - "rootfstype=jffs2\0" \ - "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "${optargs} " \ + "mpurate=${mpurate} " \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ + "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source ${loadaddr}\0" \ - "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ @@ -174,7 +188,7 @@ "bootm ${loadaddr}\0" \ #define CONFIG_BOOTCOMMAND \ - "if mmc init; then " \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ @@ -189,13 +203,10 @@ /* * Miscellaneous configurable options */ -#define V_PROMPT "Overo # " - #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#define CONFIG_SYS_PROMPT V_PROMPT -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PROMPT "Overo # " +#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) @@ -219,28 +230,13 @@ #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ #define CONFIG_SYS_HZ 1000 -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE SZ_128K /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ -#endif - /*----------------------------------------------------------------------- * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 -/* SDRAM Bank Allocation method */ -#define SDRC_R_B_C 1 - /*----------------------------------------------------------------------- * FLASH and environment organization */ @@ -251,60 +247,94 @@ #define PISMO1_NAND_SIZE GPMC_SIZE_128M #define PISMO1_ONEN_SIZE GPMC_SIZE_128M -#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ - /* one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ -#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ -#define CONFIG_SYS_FLASH_BASE boot_flash_base +#if defined(CONFIG_CMD_NAND) +#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE +#endif /* Monitor at start of flash */ #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP -#define CONFIG_ENV_IS_IN_NAND 1 +#define CONFIG_ENV_IS_IN_NAND #define ONENAND_ENV_OFFSET 0x240000 /* environment starts here */ #define SMNAND_ENV_OFFSET 0x240000 /* environment starts here */ -#define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec -#define CONFIG_ENV_OFFSET boot_flash_off +#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ +#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET -/*----------------------------------------------------------------------- - * CFI FLASH driver setup - */ -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) -#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) - -/* Flash banks JFFS2 should use */ -#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ - CONFIG_SYS_MAX_NAND_DEVICE) -#define CONFIG_SYS_JFFS2_MEM_NAND -/* use flash_info[2] */ -#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 - -#ifndef __ASSEMBLY__ -extern struct gpmc *gpmc_cfg; -extern unsigned int boot_flash_base; -extern volatile unsigned int boot_flash_env_addr; -extern unsigned int boot_flash_off; -extern unsigned int boot_flash_sec; -extern unsigned int boot_flash_type; -#endif - #if defined(CONFIG_CMD_NET) /*---------------------------------------------------------------------------- * SMSC9211 Ethernet from SMSC9118 family *---------------------------------------------------------------------------- */ -#define CONFIG_NET_MULTI -#define CONFIG_SMC911X 1 +#define CONFIG_SMC911X #define CONFIG_SMC911X_32_BIT -#define CONFIG_SMC911X_BASE 0x2C000000 +#define CONFIG_SMC911X_BASE 0x2C000000 #endif /* (CONFIG_CMD_NET) */ +/* + * Leave it at 0x80008000 to allow booting new u-boot.bin with X-loader + * and older u-boot.bin with the new U-Boot SPL. + */ +#define CONFIG_SYS_TEXT_BASE 0x80008000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 +#define CONFIG_SYS_INIT_RAM_SIZE 0x800 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_FRAMEWORK +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_TEXT_BASE 0x40200800 +#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +/* move malloc and bss high to prevent clashing with the main image */ +#define CONFIG_SYS_SPL_MALLOC_START 0x87000000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 +#define CONFIG_SPL_BSS_START_ADDR 0x87080000 /* end of minimum RAM */ +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +#define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" + +/* NAND boot config */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + #endif /* __CONFIG_H */