X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fomap3_sdp3430.h;h=1ca79d4ee4ddf3a4ed291901ebadacb6f955b93d;hb=e390bd5ed06fcd29743a3728e9facc4891d094fa;hp=836a3d847d1c86c40bc0153e5b5b6e63b91e8a5d;hpb=c2120fbfbc4d1f6953228f86be8bdbf38bacfdab;p=u-boot diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h index 836a3d847d..1ca79d4ee4 100644 --- a/include/configs/omap3_sdp3430.h +++ b/include/configs/omap3_sdp3430.h @@ -7,7 +7,7 @@ * * Configuration settings for the 3430 TI SDP3430 board. * - * SPDX-License-Identifier: GPL-2.0+ + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -16,18 +16,22 @@ /* TODO: REMOVE THE FOLLOWING * Retained the following till size.h is removed in u-boot */ -#include +#include /* * High Level Configuration Options */ #define CONFIG_OMAP 1 /* in a TI OMAP core */ -#define CONFIG_OMAP34XX 1 /* which is a 34XX */ #define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */ +#define CONFIG_OMAP_COMMON +/* Common ARM Erratas */ +#define CONFIG_ARM_ERRATA_454179 +#define CONFIG_ARM_ERRATA_430973 +#define CONFIG_ARM_ERRATA_621766 #define CONFIG_SDRC /* The chip has SDRC controller */ #include /* get chip and board defs */ -#include +#include /* * NOTE: these #defines presume standard SDP jumper settings. @@ -113,10 +117,10 @@ /* * I2C for power management setup */ -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_OMAP24_I2C_SPEED 100000 +#define CONFIG_SYS_OMAP24_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_OMAP34XX /* OMITTED: single 1 Gbit MT29F1G NAND flash */ @@ -272,7 +276,6 @@ */ #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800