X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fp1_p2_rdb_pc.h;h=2fa537291b2bb0aceb3032f30740215e211df0b0;hb=f9c1456cf632175afb7d6b27f42f1aab8432be0f;hp=964bfcd440bed222e46e74053a320534b4ffff87;hpb=96764df1b47ddebfb50fadf5af72530b07b5fc89;p=u-boot

diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 964bfcd440..2fa537291b 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -164,7 +164,7 @@
 #define CONFIG_SPL_TARGET		"u-boot-with-spl.bin"
 
 #define CONFIG_SPL_TEXT_BASE		0xfffff000
-#define CONFIG_SPL_MAX_SIZE		(4 * 1024)
+#define CONFIG_SPL_MAX_SIZE		4096
 
 #ifdef CONFIG_SYS_INIT_L2_ADDR
 /* We multiply CONFIG_SPL_MAX_SIZE by two to leave some room for BSS. */
@@ -217,6 +217,7 @@
 #define CONFIG_PCIE1	/* PCIE controler 1 (slot 1) */
 #define CONFIG_PCIE2	/* PCIE controler 2 (slot 2) */
 #define CONFIG_FSL_PCI_INIT	/* Use common FSL init code */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
 #define CONFIG_FSL_PCIE_RESET	/* need PCIe reset errata */
 #define CONFIG_SYS_PCI_64BIT	/* enable 64-bit PCI resources */