X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fpalmtc.h;h=6e8d8e9d573398b2a25ef08475ef8e94f6db37da;hb=833b6435de3e8cf5b06ba81cb1b2b50e044269ff;hp=40ab0bf2c094292eb211669604b412f8930b2a9f;hpb=90d8cff09918f1fdf15cdb4e6c55fb1712340710;p=u-boot

diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h
index 40ab0bf2c0..6e8d8e9d57 100644
--- a/include/configs/palmtc.h
+++ b/include/configs/palmtc.h
@@ -27,7 +27,7 @@
 /*
  * High Level Board Configuration Options
  */
-#define	CONFIG_PXA250			1	/* Intel PXA255 CPU */
+#define	CONFIG_CPU_PXA25X			1	/* Intel PXA255 CPU */
 #define	CONFIG_PALMTC			1	/* Palm Tungsten|C board */
 
 /*
@@ -35,7 +35,6 @@
  */
 #define	CONFIG_ENV_OVERWRITE
 #define	CONFIG_SYS_MALLOC_LEN		(128*1024)
-#define	CONFIG_SYS_GBL_DATA_SIZE	128
 #define	CONFIG_SYS_TEXT_BASE	0x0
 
 #define	CONFIG_BOOTCOMMAND						\
@@ -59,8 +58,8 @@
  */
 #define	CONFIG_PXA_SERIAL
 #define	CONFIG_FFUART			1
+#define CONFIG_CONS_INDEX		3
 #define	CONFIG_BAUDRATE			115200
-#define	CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Bootloader Components Configuration
@@ -68,6 +67,7 @@
 #include <config_cmd_default.h>
 
 #undef	CONFIG_CMD_NET
+#undef	CONFIG_CMD_NFS
 #define	CONFIG_CMD_ENV
 #define	CONFIG_CMD_MMC
 #define	CONFIG_LCD
@@ -110,7 +110,6 @@
  * HUSH Shell Configuration
  */
 #define	CONFIG_SYS_HUSH_PARSER		1
-#define	CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 #define	CONFIG_SYS_LONGHELP
 #ifdef	CONFIG_SYS_HUSH_PARSER
@@ -132,15 +131,6 @@
 #define	CONFIG_SYS_HZ			3686400		/* Timer @ 3686400 Hz */
 #define	CONFIG_SYS_CPUSPEED		0x161		/* 400MHz;L=1 M=3 T=1 */
 
-/*
- * Stack sizes
- */
-#define	CONFIG_STACKSIZE		(128*1024)	/* regular stack */
-#ifdef	CONFIG_USE_IRQ
-#define	CONFIG_STACKSIZE_IRQ		(4*1024)	/* IRQ stack */
-#define	CONFIG_STACKSIZE_FIQ		(4*1024)	/* FIQ stack */
-#endif
-
 /*
  * DRAM Map
  */
@@ -157,7 +147,7 @@
 #define	CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_DRAM_BASE
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define	CONFIG_SYS_INIT_SP_ADDR		0xfffff800
 
 /*
  * NOR FLASH