X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fpleb2.h;h=2aeb7fb34e33471fc20f403601e3d1a6c51e48c4;hb=6d1d5cf96ef9d7756a741709071c9c23b8490a0c;hp=14f8917a97aba0a298117f4141095e07ef248317;hpb=f82642e33899766892499b163e60560fbbf87773;p=u-boot

diff --git a/include/configs/pleb2.h b/include/configs/pleb2.h
index 14f8917a97..2aeb7fb34e 100644
--- a/include/configs/pleb2.h
+++ b/include/configs/pleb2.h
@@ -38,27 +38,32 @@
 #define CONFIG_PLEB2		1	/* on an PLEB2 Board	    */
 #undef CONFIG_LCD
 #undef CONFIG_MMC
-#define BOARD_LATE_INIT		1
+#define CONFIG_BOARD_LATE_INIT
+#define	CONFIG_SYS_TEXT_BASE	0x0
 
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
 
+/* we will never enable dcache, because we have to setup MMU first */
+#define CONFIG_SYS_DCACHE_OFF
+
 /*
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
  */
 
 /* None - PLEB 2 doesn't have any of this.
-   #define CONFIG_DRIVER_LAN91C96
-   #define CONFIG_LAN91C96_BASE 0x0C000000 */
+	#define CONFIG_LAN91C96
+	#define CONFIG_LAN91C96_BASE 0x0C000000
+ */
 
 /*
  * select serial console configuration
  */
+#define CONFIG_PXA_SERIAL
 #define CONFIG_FFUART	       1       /* we use FFUART on PLEB 2 */
 
 /* allow to overwrite serial and ethaddr */
@@ -82,6 +87,7 @@
 #include <config_cmd_default.h>
 
 #undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
 
 
 #define CONFIG_BOOTDELAY	3
@@ -122,16 +128,19 @@
 #define CONFIG_SYS_MEMTEST_START	0xa0400000	/* memtest works on	*/
 #define CONFIG_SYS_MEMTEST_END		0xa0800000	/* 4 ... 8 MB in DRAM	*/
 
-#undef	CONFIG_SYS_CLKS_IN_HZ		/* everything, incl board info, in Hz */
-
 #define CONFIG_SYS_LOAD_ADDR		0xa2000000	/* default load address */
 
-#define CONFIG_SYS_HZ			3686400		/* incrementer freq: 3.6864 MHz */
+#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_CPUSPEED		0x141		/* set core clock to 200/200/100 MHz */
 
 						/* valid baudrates */
 #define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
+#ifdef CONFIG_MMC
+#define CONFIG_PXA_MMC
+#define CONFIG_CMD_MMC
+#endif
+
 /*
  * Stack sizes
  *
@@ -146,15 +155,9 @@
 /*
  * Physical Memory Map
  */
-#define CONFIG_NR_DRAM_BANKS	4	   /* we have 2 banks of DRAM */
+#define CONFIG_NR_DRAM_BANKS	1	   /* we have 1 bank of DRAM */
 #define PHYS_SDRAM_1		0xa0000000 /* SDRAM Bank #1 */
 #define PHYS_SDRAM_1_SIZE	0x02000000 /* 32 MB */
-#define PHYS_SDRAM_2		0xa4000000 /* SDRAM Bank #2 */
-#define PHYS_SDRAM_2_SIZE	0x00000000 /* 0 MB */
-#define PHYS_SDRAM_3		0xa8000000 /* SDRAM Bank #3 */
-#define PHYS_SDRAM_3_SIZE	0x00000000 /* 0 MB */
-#define PHYS_SDRAM_4		0xac000000 /* SDRAM Bank #4 */
-#define PHYS_SDRAM_4_SIZE	0x00000000 /* 0 MB */
 
 #define PHYS_FLASH_1		0x00000000 /* Flash Bank #1 */
 #define PHYS_FLASH_2		0x04000000 /* Flash Bank #2 */
@@ -170,6 +173,9 @@
 #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
 
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
+
 /*
  * GPIO settings
  */
@@ -201,9 +207,9 @@
 #define CONFIG_SYS_GAFR2_U_VAL		0x00000000
 
 #define CONFIG_SYS_PSSR_VAL		0x20
-#define CONFIG_SYS_CCCR_VAL	    0x00000141	/* 100 MHz memory, 200 MHz CPU	*/
-#define CONFIG_SYS_CKEN_VAL	    0x00000060	/* FFUART and STUART enabled	*/
-#define CONFIG_SYS_ICMR_VAL	    0x00000000	/* No interrupts enabled	*/
+#define CONFIG_SYS_CCCR		    0x00000141	/* 100 MHz memory, 200 MHz CPU	*/
+#define CONFIG_SYS_CKEN		    0x00000060	/* FFUART and STUART enabled	*/
+#define CONFIG_SYS_ICMR		    0x00000000	/* No interrupts enabled	*/
 
 /*
  * Memory settings
@@ -219,6 +225,9 @@
 					   /* bits set in lowlevel_init.S	*/
 #define CONFIG_SYS_MDMRS_VAL		0x00000000
 
+#define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
+#define	CONFIG_SYS_SXCNFG_VAL		0x00000000
+
 /*
  * PCMCIA and CF Interfaces
  */