X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fpm9261.h;h=10415d31a5e7191eb2f0ea46d2426b27e7bc5c6b;hb=ad970756208864de4b353b77bfb04c0fb4fc5ab5;hp=fc95cf0bfa0542093dcc8be18ae63f1927e4ab75;hpb=d44a5f51288aec60c6bdb4ac939d75c24e5bf9c2;p=u-boot

diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h
index fc95cf0bfa..10415d31a5 100644
--- a/include/configs/pm9261.h
+++ b/include/configs/pm9261.h
@@ -20,6 +20,8 @@
 #include <asm/hardware.h>
 /* ARM asynchronous clock */
 
+#define CONFIG_SYS_GENERIC_BOARD
+
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define MASTER_PLL_DIV		15
@@ -50,15 +52,13 @@
 #define	CONFIG_SYS_MCKR1_VAL		\
 		(AT91_PMC_MCKR_CSS_SLOW |	\
 		 AT91_PMC_MCKR_PRES_1 |	\
-		 AT91_PMC_MCKR_MDIV_2 |	\
-		 AT91_PMC_MCKR_PLLADIV_1)
+		 AT91_PMC_MCKR_MDIV_2)
 
 /* PCK/2 = MCK Master Clock from PLLA */
 #define	CONFIG_SYS_MCKR2_VAL		\
 		(AT91_PMC_MCKR_CSS_PLLA |	\
 		 AT91_PMC_MCKR_PRES_1 |	\
-		 AT91_PMC_MCKR_MDIV_2 |	\
-		 AT91_PMC_MCKR_PLLADIV_1)
+		 AT91_PMC_MCKR_MDIV_2)
 
 /* define PDC[31:16] as DATA[31:16] */
 #define CONFIG_SYS_PIOC_PDR_VAL1	0xFFFF0000
@@ -166,9 +166,9 @@
 
 /* LED */
 #define CONFIG_AT91_LED
-#define	CONFIG_RED_LED		AT91_PIO_PORTC, 12
-#define	CONFIG_GREEN_LED	AT91_PIO_PORTC, 13
-#define	CONFIG_YELLOW_LED	AT91_PIO_PORTC, 15
+#define CONFIG_RED_LED		GPIO_PIN_PC(12)
+#define CONFIG_GREEN_LED	GPIO_PIN_PC(13)
+#define CONFIG_YELLOW_LED	GPIO_PIN_PC(15)
 
 #define CONFIG_BOOTDELAY	3
 
@@ -204,7 +204,6 @@
 /* DataFlash */
 #define CONFIG_ATMEL_DATAFLASH_SPI
 #define CONFIG_HAS_DATAFLASH
-#define CONFIG_SYS_SPI_WRITE_TOUT		(5 * CONFIG_SYS_HZ)
 #define CONFIG_SYS_MAX_DATAFLASH_BANKS		1
 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
 #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* CS3 */
@@ -221,8 +220,8 @@
 #define CONFIG_SYS_NAND_MASK_ALE		(1 << 22)
 /* our CLE is AD21 */
 #define CONFIG_SYS_NAND_MASK_CLE		(1 << 21)
-#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIO_PORTC, 14
-#define CONFIG_SYS_NAND_READY_PIN		AT91_PIO_PORTA, 16
+#define CONFIG_SYS_NAND_ENABLE_PIN		GPIO_PIN_PC(14)
+#define CONFIG_SYS_NAND_READY_PIN		GPIO_PIN_PA(16)
 
 /* NOR flash */
 #define CONFIG_SYS_FLASH_CFI			1