X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fpm9263.h;h=43104a3e282f9652725b872c691c129e7f0dc400;hb=0c2dd9a05bdcf3b2b4880509ec690116873fe158;hp=0db17b3545a316222f32aed6fff7ecb78c27008e;hpb=6ebff365eb63093ca35b687316002535c6a18820;p=u-boot diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index 0db17b3545..43104a3e28 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -28,60 +28,100 @@ #ifndef __CONFIG_H #define __CONFIG_H -/* ARM asynchronous clock */ -#define AT91_CPU_NAME "AT91SAM9263" +/* + * SoC must be defined first, before hardware.h is included. + * In this case SoC is defined in boards.cfg. + */ +#include +/* ARM asynchronous clock */ +#define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -#define MASTER_PLL_DIV 15 -#define MASTER_PLL_MUL 162 +#define MASTER_PLL_DIV 6 +#define MASTER_PLL_MUL 65 #define MAIN_PLL_DIV 2 /* 2 or 4 */ -#define AT91_MAIN_CLOCK 18432000 +#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ #define CONFIG_SYS_HZ 1000 -#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ -#define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/ +#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9263" #define CONFIG_PM9263 1 /* on a Ronetix PM9263 Board */ #define CONFIG_ARCH_CPU_INIT #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#define CONFIG_SYS_TEXT_BASE 0 + +#define MACH_TYPE_PM9263 1475 +#define CONFIG_MACH_TYPE MACH_TYPE_PM9263 /* clocks */ -#define CONFIG_SYS_MOR_VAL 0x00002001 /* CKGR_MOR - enable main osc. */ -#define CONFIG_SYS_PLLAR_VAL \ - (0x2000BF00 | ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) +#define CONFIG_SYS_MOR_VAL \ + (AT91_PMC_MOR_MOSCEN | \ + (255 << 8)) /* Main Oscillator Start-up Time */ +#define CONFIG_SYS_PLLAR_VAL \ + (AT91_PMC_PLLAR_29 | /* Bit 29 must be 1 when prog */ \ + AT91_PMC_PLLXR_OUT(3) | \ + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | /* PLL Counter */\ + (2 << 28) | /* PLL Clock Frequency Range */ \ + ((MASTER_PLL_MUL - 1) << 16) | (MASTER_PLL_DIV)) #if (MAIN_PLL_DIV == 2) /* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL 0x00000100 +#define CONFIG_SYS_MCKR1_VAL \ + (AT91_PMC_MCKR_CSS_SLOW | \ + AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_2) /* PCK/2 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL 0x00000102 +#define CONFIG_SYS_MCKR2_VAL \ + (AT91_PMC_MCKR_CSS_PLLA | \ + AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_2) #else /* PCK/4 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR1_VAL 0x00000200 +#define CONFIG_SYS_MCKR1_VAL \ + (AT91_PMC_MCKR_CSS_SLOW | \ + AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_4) /* PCK/4 = MCK Master Clock from PLLA */ -#define CONFIG_SYS_MCKR2_VAL 0x00000202 +#define CONFIG_SYS_MCKR2_VAL \ + (AT91_PMC_MCKR_CSS_PLLA | \ + AT91_PMC_MCKR_PRES_1 | \ + AT91_PMC_MCKR_MDIV_4) #endif /* define PDC[31:16] as DATA[31:16] */ #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 /* no pull-up for D[31:16] */ #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ -#define CONFIG_SYS_MATRIX_EBI0CSA_VAL 0x0001010A -/* EBI1_CSA, 3.3v, no pull-ups */ -#define CONFIG_SYS_MATRIX_EBI1CSA_VAL 0x00010100 +#define CONFIG_SYS_MATRIX_EBI0CSA_VAL \ + (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ + AT91_MATRIX_CSA_EBI_CS1A) /* SDRAM */ /* SDRAMC_MR Mode register */ #define CONFIG_SYS_SDRC_MR_VAL1 0 /* SDRAMC_TR - Refresh Timer register */ -#define CONFIG_SYS_SDRC_TR_VAL1 0x13C -#define CONFIG_SYS_SDRC_CR_VAL 0x85227279 /*CL3*/ +#define CONFIG_SYS_SDRC_TR_VAL1 0x3AA +/* SDRAMC_CR - Configuration register*/ +#define CONFIG_SYS_SDRC_CR_VAL \ + (AT91_SDRAMC_NC_9 | \ + AT91_SDRAMC_NR_13 | \ + AT91_SDRAMC_NB_4 | \ + AT91_SDRAMC_CAS_2 | \ + AT91_SDRAMC_DBW_32 | \ + (2 << 8) | /* tWR - Write Recovery Delay */ \ + (7 << 12) | /* tRC - Row Cycle Delay */ \ + (2 << 16) | /* tRP - Row Precharge Delay */ \ + (2 << 20) | /* tRCD - Row to Column Delay */ \ + (5 << 24) | /* tRAS - Active to Precharge Delay */ \ + (8 << 28)) /* tXSR - Exit Self Refresh to Active Delay */ + /* Memory Device Register -> SDRAM */ -#define CONFIG_SYS_SDRC_MDR_VAL 0 -#define CONFIG_SYS_SDRC_MR_VAL2 0x00000002 /* SDRAMC_MR */ +#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM +#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL3 4 /* SDRC_MR */ +#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ @@ -90,48 +130,56 @@ #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL4 3 /* SDRC_MR */ +#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ -#define CONFIG_SYS_SDRC_MR_VAL5 0 /* SDRC_MR */ +#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ -#define CONFIG_SYS_SMC0_SETUP0_VAL 0x0A0A0A0A /* SMC_SETUP */ -#define CONFIG_SYS_SMC0_PULSE0_VAL 0x0B0B0B0B /* SMC_PULSE */ -#define CONFIG_SYS_SMC0_CYCLE0_VAL 0x00160016 /* SMC_CYCLE */ -#define CONFIG_SYS_SMC0_CTRL0_VAL 0x00161003 /* SMC_MODE */ - -/* setup SMC1, CS0 (PSRAM) - 16-bit */ -#define CONFIG_SYS_SMC1_SETUP0_VAL 0x00000000 /* SMC_SETUP */ -#define CONFIG_SYS_SMC1_PULSE0_VAL 0x07020707 /* SMC_PULSE */ -#define CONFIG_SYS_SMC1_CYCLE0_VAL 0x00080008 /* SMC_CYCLE */ -#define CONFIG_SYS_SMC1_CTRL0_VAL 0x31001000 /* SMC_MODE */ - -#define CONFIG_SYS_RSTC_RMR_VAL 0xA5000301 /* user reset enable */ - -/* Watchdog */ -#define CONFIG_SYS_WDTC_WDMR_VAL 0x3fff8fff /* disable watchdog */ - -/* */ +#define CONFIG_SYS_SMC0_SETUP0_VAL \ + (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ + AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) +#define CONFIG_SYS_SMC0_PULSE0_VAL \ + (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ + AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) +#define CONFIG_SYS_SMC0_CYCLE0_VAL \ + (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) +#define CONFIG_SYS_SMC0_MODE0_VAL \ + (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ + AT91_SMC_MODE_DBW_16 | \ + AT91_SMC_MODE_TDF | \ + AT91_SMC_MODE_TDF_CYCLE(6)) + +/* user reset enable */ +#define CONFIG_SYS_RSTC_RMR_VAL \ + (AT91_RSTC_KEY | \ + AT91_RSTC_CR_PROCRST | \ + AT91_RSTC_MR_ERSTL(1) | \ + AT91_RSTC_MR_ERSTL(2)) + +/* Disable Watchdog */ +#define CONFIG_SYS_WDTC_WDMR_VAL \ + (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ + AT91_WDT_MR_WDV(0xfff) | \ + AT91_WDT_MR_WDDIS | \ + AT91_WDT_MR_WDD(0xfff)) #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_INITRD_TAG 1 #undef CONFIG_SKIP_LOWLEVEL_INIT -#undef CONFIG_SKIP_RELOCATE_UBOOT #define CONFIG_USER_LOWLEVEL_INIT 1 /* * Hardware drivers */ +#define CONFIG_AT91_GPIO 1 #define CONFIG_ATMEL_USART 1 -#undef CONFIG_USART0 -#undef CONFIG_USART1 -#undef CONFIG_USART2 -#define CONFIG_USART3 1 /* USART 3 is DBGU */ +#define CONFIG_USART_BASE ATMEL_BASE_DBGU +#define CONFIG_USART_ID ATMEL_ID_SYS /* LCD */ #define CONFIG_LCD 1 @@ -149,8 +197,8 @@ /* LED */ #define CONFIG_AT91_LED -#define CONFIG_RED_LED AT91_PIN_PB7 /* this is the power led */ -#define CONFIG_GREEN_LED AT91_PIN_PB8 /* this is the user1 led */ +#define CONFIG_RED_LED AT91_PIO_PORTB, 7 /* this is the power led */ +#define CONFIG_GREEN_LED AT91_PIO_PORTB, 8 /* this is the user1 led */ #define CONFIG_BOOTDELAY 3 @@ -168,11 +216,11 @@ #include #undef CONFIG_CMD_BDI #undef CONFIG_CMD_IMI -#undef CONFIG_CMD_AUTOSCRIPT #undef CONFIG_CMD_FPGA #undef CONFIG_CMD_LOADS #undef CONFIG_CMD_IMLS +#define CONFIG_CMD_CACHE #define CONFIG_CMD_PING 1 #define CONFIG_CMD_DHCP 1 #define CONFIG_CMD_NAND 1 @@ -212,8 +260,9 @@ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* our CLE is AD22 */ #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) -#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 -#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PB30 +#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIO_PORTD, 15 +#define CONFIG_SYS_NAND_READY_PIN AT91_PIO_PORTB, 30 + #endif #define CONFIG_CMD_JFFS2 1 @@ -226,11 +275,15 @@ /* PSRAM */ #define PHYS_PSRAM 0x70000000 #define PHYS_PSRAM_SIZE 0x00400000 /* 4MB */ +/* Slave EBI1, PSRAM connected */ +#define CONFIG_PSRAM_SCFG (AT91_MATRIX_SCFG_ARBT_FIXED_PRIORITY | \ + AT91_MATRIX_SCFG_FIXED_DEFMSTR(5) | \ + AT91_MATRIX_SCFG_DEFMSTR_TYPE_FIXED | \ + AT91_MATRIX_SCFG_SLOT_CYCLE(255)) /* Ethernet */ #define CONFIG_MACB 1 #define CONFIG_RMII 1 -#define CONFIG_NET_MULTI 1 #define CONFIG_NET_RETRY_COUNT 20 #define CONFIG_RESET_PHY_R 1 @@ -264,7 +317,7 @@ #define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ "root=/dev/mtdblock0 " \ - "mtdparts=at91_nand:-(root) "\ + "mtdparts=atmel_nand:-(root) "\ "rw rootfstype=jffs2" #elif defined(CONFIG_SYS_USE_NANDFLASH) /* CFG_USE_NANDFLASH */ @@ -277,7 +330,7 @@ #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ "root=/dev/mtdblock5 " \ - "mtdparts=at91_nand:" \ + "mtdparts=atmel_nand:" \ "128k(bootstrap)ro," \ "256k(uboot)ro," \ "128k(env1)ro," \ @@ -302,7 +355,7 @@ #define CONFIG_SYS_JFFS2_FIRST_SECTOR 11 #define CONFIG_BOOTCOMMAND "run flashboot" -#define CONFIG_ROOTPATH /ronetix/rootfs +#define CONFIG_ROOTPATH "/ronetix/rootfs" #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n" #define CONFIG_CON_ROT "fbcon=rotate:3 " @@ -351,12 +404,14 @@ #define CONFIG_SYS_LONGHELP 1 #define CONFIG_CMDLINE_EDITING 1 -#define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) /* * Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128 * 1024, 0x1000) -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ + GENERATED_GBL_DATA_SIZE) #define CONFIG_STACKSIZE (32 * 1024) /* regular stack */