X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fpm9g45.h;h=c766330bb2260854ba9004cec0c4dfc9728241e6;hb=f3fcf92d595b297b47a1b58b8ec39f93f40ef912;hp=2fbe5c66a9f1c1a532cad4ee3ba6d8280cb8e371;hpb=25ddd1fb0a2281b182529afbc8fda5de2dc16d96;p=u-boot

diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h
index 2fbe5c66a9..c766330bb2 100644
--- a/include/configs/pm9g45.h
+++ b/include/configs/pm9g45.h
@@ -5,7 +5,7 @@
  * Ronetix GmbH <www.ronetix.at>
  *
  * (C) Copyright 2007-2008
- * Stelian Pop <stelian.pop@leadtechdesign.com>
+ * Stelian Pop <stelian@popies.net>
  * Lead Tech Design <www.leadtechdesign.com>
  *
  * Configuation settings for the PM9G45 board.
@@ -32,13 +32,23 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core */
+/*
+ * SoC must be defined first, before hardware.h is included.
+ * In this case SoC is defined in boards.cfg.
+ */
+#include <asm/hardware.h>
+
 #define CONFIG_PM9G45		1	/* It's an Ronetix PM9G45 */
-#define CONFIG_AT91SAM9G45	1	/* It's an Atmel AT91SAM9G45 SoC */
+#define CONFIG_SYS_AT91_CPU_NAME	"AT91SAM9G45"
+
+#define MACH_TYPE_PM9G45	2672
+#define CONFIG_MACH_TYPE	MACH_TYPE_PM9G45
 
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_MAIN_CLOCK	12000000 /* from 12 MHz crystal */
+#define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
 #define CONFIG_SYS_HZ			1000
+#define CONFIG_SYS_TEXT_BASE		0x73f00000
 
 #define CONFIG_ARCH_CPU_INIT
 
@@ -47,14 +57,15 @@
 #define CONFIG_INITRD_TAG	1
 
 #define CONFIG_SKIP_LOWLEVEL_INIT
-#define CONFIG_SKIP_RELOCATE_UBOOT
+#define CONFIG_BOARD_EARLY_INIT_F
 
 /*
  * Hardware drivers
  */
 #define CONFIG_AT91_GPIO	1
 #define CONFIG_ATMEL_USART	1
-#define CONFIG_USART3		1	/* USART 3 is DBGU */
+#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
+#define	CONFIG_USART_ID			ATMEL_ID_SYS
 
 #define CONFIG_SYS_USE_NANDFLASH	1
 
@@ -80,6 +91,7 @@
 #undef CONFIG_CMD_FPGA
 #undef CONFIG_CMD_IMLS
 
+#define CONFIG_CMD_CACHE
 #define CONFIG_CMD_PING		1
 #define CONFIG_CMD_DHCP		1
 #define CONFIG_CMD_NAND		1
@@ -103,7 +115,6 @@
 
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
-#define CONFIG_NAND_MAX_CHIPS		1
 #define CONFIG_NAND_ATMEL
 #define CONFIG_SYS_MAX_NAND_DEVICE	1
 #define CONFIG_SYS_NAND_BASE		0x40000000
@@ -120,7 +131,6 @@
 /* Ethernet */
 #define CONFIG_MACB			1
 #define CONFIG_RMII			1
-#define CONFIG_NET_MULTI		1
 #define CONFIG_NET_RETRY_COUNT		20
 #define CONFIG_RESET_PHY_R		1
 
@@ -157,7 +167,6 @@
 				"rootfstype=jffs2"
 
 #define CONFIG_BAUDRATE			115200
-#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }
 
 #define CONFIG_SYS_PROMPT		"U-Boot> "
 #define CONFIG_SYS_CBSIZE		256
@@ -168,7 +177,6 @@
 #define CONFIG_CMDLINE_EDITING		1
 #define CONFIG_AUTO_COMPLETE
 #define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 /*
  * Size of malloc() pool
@@ -176,6 +184,10 @@
 #define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024,\
 					0x1000)
 
+#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM
+#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x1000 - \
+				GENERATED_GBL_DATA_SIZE)
+
 #define CONFIG_STACKSIZE		(32*1024)	/* regular stack */
 
 #ifdef CONFIG_USE_IRQ