X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fpxa255_idp.h;h=ce9e7d115d8af6f17018fc3c0bda0745d3933257;hb=3d6ba91e793808d1612152e9f9b8c51b3ca6c926;hp=1afff5e23d794a96d5280d921a1a314cbf9f958f;hpb=225f0eaa745adfae05931848543d99942798756a;p=u-boot diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h index 1afff5e23d..ce9e7d115d 100644 --- a/include/configs/pxa255_idp.h +++ b/include/configs/pxa255_idp.h @@ -42,7 +42,7 @@ * so we MUST NOT initialize critical regs like mem-timing ... */ #undef CONFIG_SKIP_LOWLEVEL_INIT /* define for developing */ -#undef CONFIG_SKIP_RELOCATE_UBOOT /* define for developing */ +#define CONFIG_SYS_TEXT_BASE 0x0 /* * define the following to enable debug blinks. A debug blink function @@ -55,7 +55,7 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ +#define CONFIG_CPU_PXA25X 1 /* This is an PXA250 CPU */ #undef CONFIG_LCD #ifdef CONFIG_LCD @@ -64,15 +64,15 @@ #define CONFIG_MMC 1 #define CONFIG_DOS_PARTITION 1 -#define BOARD_LATE_INIT 1 +#define CONFIG_BOARD_LATE_INIT -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/* we will never enable dcache, because we have to setup MMU first */ +#define CONFIG_SYS_DCACHE_OFF /* * Size of malloc() pool */ -#define CFG_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) -#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) /* * PXA250 IDP memory map information @@ -84,7 +84,7 @@ /* * Hardware drivers */ -#define CONFIG_DRIVER_SMC91111 +#define CONFIG_SMC91111 #define CONFIG_SMC91111_BASE (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300) #define CONFIG_SMC_USE_32_BIT 1 /* #define CONFIG_SMC_USE_IOFUNCS */ @@ -97,6 +97,7 @@ /* * select serial console configuration */ +#define CONFIG_PXA_SERIAL #define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */ /* allow to overwrite serial and ethaddr */ @@ -119,7 +120,6 @@ */ #include -#define CONFIG_CMD_MMC #define CONFIG_CMD_FAT #define CONFIG_CMD_DHCP @@ -219,53 +219,40 @@ /* * Miscellaneous configurable options */ -#define CFG_HUSH_PARSER 1 -#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_HUSH_PARSER 1 -#define CFG_LONGHELP /* undef to save memory */ -#ifdef CFG_HUSH_PARSER -#define CFG_PROMPT "$ " /* Monitor Command Prompt */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ #else -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #endif -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_DEVICE_NULLDEV 1 - -#define CFG_MEMTEST_START 0xa0400000 /* memtest works on */ -#define CFG_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_DEVICE_NULLDEV 1 -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ +#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ -#define CFG_LOAD_ADDR 0xa0800000 /* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0xa0800000 /* default load address */ -#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */ -#define CFG_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ #define RTC 1 /* enable 32KHz osc */ - /* valid baudrates */ -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -#define CFG_MMC_BASE 0xF0000000 - -/* - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ -#ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#ifdef CONFIG_MMC +#define CONFIG_PXA_MMC +#define CONFIG_CMD_MMC +#define CONFIG_SYS_MMC_BASE 0xF0000000 #endif /* * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 4 /* we have 1 banks of DRAM */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ #define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ @@ -281,71 +268,79 @@ #define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ #define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ -#define CFG_DRAM_BASE 0xa0000000 -#define CFG_DRAM_SIZE 0x04000000 +#define CONFIG_SYS_DRAM_BASE 0xa0000000 +#define CONFIG_SYS_DRAM_SIZE 0x04000000 + +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800 /* * GPIO settings */ -#define CFG_GAFR0_L_VAL 0x80001005 -#define CFG_GAFR0_U_VAL 0xa5128012 -#define CFG_GAFR1_L_VAL 0x699a9558 -#define CFG_GAFR1_U_VAL 0xaaa5aa6a -#define CFG_GAFR2_L_VAL 0xaaaaaaaa -#define CFG_GAFR2_U_VAL 0x2 -#define CFG_GPCR0_VAL 0x1800400 -#define CFG_GPCR1_VAL 0x0 -#define CFG_GPCR2_VAL 0x0 -#define CFG_GPDR0_VAL 0xc1818440 -#define CFG_GPDR1_VAL 0xfcffab82 -#define CFG_GPDR2_VAL 0x1ffff -#define CFG_GPSR0_VAL 0x8000 -#define CFG_GPSR1_VAL 0x3f0002 -#define CFG_GPSR2_VAL 0x1c000 - -#define CFG_PSSR_VAL 0x20 +#define CONFIG_SYS_GAFR0_L_VAL 0x80001005 +#define CONFIG_SYS_GAFR0_U_VAL 0xa5128012 +#define CONFIG_SYS_GAFR1_L_VAL 0x699a9558 +#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5aa6a +#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa +#define CONFIG_SYS_GAFR2_U_VAL 0x2 +#define CONFIG_SYS_GPCR0_VAL 0x1800400 +#define CONFIG_SYS_GPCR1_VAL 0x0 +#define CONFIG_SYS_GPCR2_VAL 0x0 +#define CONFIG_SYS_GPDR0_VAL 0xc1818440 +#define CONFIG_SYS_GPDR1_VAL 0xfcffab82 +#define CONFIG_SYS_GPDR2_VAL 0x1ffff +#define CONFIG_SYS_GPSR0_VAL 0x8000 +#define CONFIG_SYS_GPSR1_VAL 0x3f0002 +#define CONFIG_SYS_GPSR2_VAL 0x1c000 + +#define CONFIG_SYS_PSSR_VAL 0x20 + +#define CONFIG_SYS_CCCR CCCR_L27|CCCR_M2|CCCR_N10 +#define CONFIG_SYS_CKEN 0x0 /* * Memory settings */ -#define CFG_MSC0_VAL 0x29DCA4D2 -#define CFG_MSC1_VAL 0x43AC494C -#define CFG_MSC2_VAL 0x39D449D4 -#define CFG_MDCNFG_VAL 0x090009C9 -#define CFG_MDREFR_VAL 0x0085C017 -#define CFG_MDMRS_VAL 0x00220022 +#define CONFIG_SYS_MSC0_VAL 0x29DCA4D2 +#define CONFIG_SYS_MSC1_VAL 0x43AC494C +#define CONFIG_SYS_MSC2_VAL 0x39D449D4 +#define CONFIG_SYS_MDCNFG_VAL 0x090009C9 +#define CONFIG_SYS_MDREFR_VAL 0x0085C017 +#define CONFIG_SYS_MDMRS_VAL 0x00220022 +#define CONFIG_SYS_FLYCNFG_VAL 0x00000000 +#define CONFIG_SYS_SXCNFG_VAL 0x00000000 /* * PCMCIA and CF Interfaces */ -#define CFG_MECR_VAL 0x00000003 -#define CFG_MCMEM0_VAL 0x00014405 -#define CFG_MCMEM1_VAL 0x00014405 -#define CFG_MCATT0_VAL 0x00014405 -#define CFG_MCATT1_VAL 0x00014405 -#define CFG_MCIO0_VAL 0x00014405 -#define CFG_MCIO1_VAL 0x00014405 +#define CONFIG_SYS_MECR_VAL 0x00000003 +#define CONFIG_SYS_MCMEM0_VAL 0x00014405 +#define CONFIG_SYS_MCMEM1_VAL 0x00014405 +#define CONFIG_SYS_MCATT0_VAL 0x00014405 +#define CONFIG_SYS_MCATT1_VAL 0x00014405 +#define CONFIG_SYS_MCIO0_VAL 0x00014405 +#define CONFIG_SYS_MCIO1_VAL 0x00014405 /* * FLASH and environment organization */ -#define CFG_FLASH_CFI +#define CONFIG_SYS_FLASH_CFI #define CONFIG_FLASH_CFI_DRIVER 1 -#define CFG_MONITOR_BASE 0 -#define CFG_MONITOR_LEN PHYS_FLASH_SECT_SIZE +#define CONFIG_SYS_MONITOR_BASE 0 +#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ -#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* timeout values are in ticks */ -#define CFG_FLASH_ERASE_TOUT (25*CFG_HZ) /* Timeout for Flash Erase */ -#define CFG_FLASH_WRITE_TOUT (25*CFG_HZ) /* Timeout for Flash Write */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */ /* put cfg at end of flash for now */ #define CONFIG_ENV_IS_IN_FLASH 1