X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fqong.h;h=685c618c346c89609e207ff4f3f1746a217098b7;hb=41d910118cfd30c802e037bab70754fbe5f04c7e;hp=485e1b1f043430f071745f16d1e5c5f4bc8118dc;hpb=a6f0c4faa4c65a7b7048b12c9d180d7e1aad1721;p=u-boot

diff --git a/include/configs/qong.h b/include/configs/qong.h
index 485e1b1f04..685c618c34 100644
--- a/include/configs/qong.h
+++ b/include/configs/qong.h
@@ -28,8 +28,6 @@
 #define CONFIG_ARM1136			/* This is an arm1136 CPU core */
 #define CONFIG_MX31			/* in a mx31 */
 #define CONFIG_QONG
-#define CONFIG_MX31_HCLK_FREQ	26000000	/* 26MHz */
-#define CONFIG_MX31_CLK32	32768
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
@@ -54,15 +52,16 @@
 
 #define CONFIG_MXC_GPIO
 #define CONFIG_HW_WATCHDOG
+#define CONFIG_IMX_WATCHDOG
 
 #define CONFIG_MXC_SPI
 #define CONFIG_DEFAULT_SPI_BUS	1
 #define CONFIG_DEFAULT_SPI_MODE	(SPI_MODE_0 | SPI_CS_HIGH)
 #define CONFIG_RTC_MC13XXX
 
-#define CONFIG_PMIC
-#define CONFIG_PMIC_SPI
-#define CONFIG_PMIC_FSL
+#define CONFIG_POWER
+#define CONFIG_POWER_SPI
+#define CONFIG_POWER_FSL
 #define CONFIG_FSL_PMIC_BUS	1
 #define CONFIG_FSL_PMIC_CS	0
 #define CONFIG_FSL_PMIC_CLK	100000
@@ -146,9 +145,6 @@
 
 #define CONFIG_LOADADDR		0x80800000	/* loadaddr env var */
 
-#define xstr(s)	str(s)
-#define str(s)	#s
-
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
@@ -178,10 +174,10 @@
 		"bootm\0"						\
 	"bootcmd=run flash_self\0"					\
 	"load=tftp ${loadaddr} ${u-boot}\0"				\
-	"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE)		\
-		" +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE)	\
+	"update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)	\
+		" +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
 		" +${filesize};cp.b ${fileaddr} "			\
-		xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"		\
+		__stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"	\
 	"upd=run load update\0"						\
 	"videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000,"	\
 		"le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296,"	\