X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fsmdk6400.h;h=04caeef968df1f02fd74964754a77b49d4e8ac0e;hb=f3fcf92d595b297b47a1b58b8ec39f93f40ef912;hp=f89fc3ef8f8bfd5b9b54b4c03fa87937beedab83;hpb=25ddd1fb0a2281b182529afbc8fda5de2dc16d96;p=u-boot

diff --git a/include/configs/smdk6400.h b/include/configs/smdk6400.h
index f89fc3ef8f..04caeef968 100644
--- a/include/configs/smdk6400.h
+++ b/include/configs/smdk6400.h
@@ -40,12 +40,15 @@
 #define CONFIG_S3C64XX		1	/* in a SAMSUNG S3C64XX Family  */
 #define CONFIG_SMDK6400		1	/* on a SAMSUNG SMDK6400 Board  */
 
-#define CONFIG_SKIP_RELOCATE_UBOOT
-
 #define CONFIG_PERIPORT_REMAP
 #define CONFIG_PERIPORT_BASE	0x70000000
 #define CONFIG_PERIPORT_SIZE	0x13
 
+#define CONFIG_SYS_IRAM_BASE    0x0c000000  /* Internal SRAM base address */
+#define CONFIG_SYS_IRAM_SIZE    0x2000      /* 8 KB of internal SRAM memory */
+#define CONFIG_SYS_IRAM_END     (CONFIG_SYS_IRAM_BASE + CONFIG_SYS_IRAM_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_IRAM_END - GENERATED_GBL_DATA_SIZE)
+
 #define CONFIG_SYS_SDRAM_BASE	0x50000000
 
 /* input clock of PLL: SMDK6400 has 12MHz input clock */
@@ -62,7 +65,7 @@
 /*
  * Architecture magic and machine type
  */
-#define MACH_TYPE		1270
+#define CONFIG_MACH_TYPE		1270
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
@@ -75,7 +78,6 @@
 /*
  * Hardware drivers
  */
-#define CONFIG_NET_MULTI
 #define CONFIG_CS8900			/* we have a CS8900 on-board	*/
 #define CONFIG_CS8900_BASE	  	0x18800300
 #define CONFIG_CS8900_BUS16		/* follow the Linux driver	*/
@@ -86,9 +88,6 @@
 #define CONFIG_SERIAL1          1	/* we use SERIAL 1 on SMDK6400	*/
 
 #define CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
-#endif
 
 #define CONFIG_CMDLINE_EDITING
 
@@ -142,9 +141,6 @@
 
 #define CONFIG_SYS_HZ			1000
 
-/* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
 /*-----------------------------------------------------------------------
  * Stack sizes
  *
@@ -260,12 +256,8 @@
 #define CONFIG_SYS_NAND_ECCSIZE	CONFIG_SYS_NAND_PAGE_SIZE
 /* Number of ECC bytes per OOB - S3C6400 calculates 4 bytes ECC in 1-bit mode */
 #define CONFIG_SYS_NAND_ECCBYTES	4
-/* Number of ECC-blocks per NAND page */
-#define CONFIG_SYS_NAND_ECCSTEPS	(CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
 /* Size of a single OOB region */
 #define CONFIG_SYS_NAND_OOBSIZE	64
-/* Number of ECC bytes per page */
-#define CONFIG_SYS_NAND_ECCTOTAL	(CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
 /* ECC byte positions */
 #define CONFIG_SYS_NAND_ECCPOS		{40, 41, 42, 43, 44, 45, 46, 47, \
 				 48, 49, 50, 51, 52, 53, 54, 55, \