X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fsocfpga_common.h;h=6d9347204b225a89a444e6ac84837dc654681efe;hb=d283a5709d8e2bf2682a2e22fb81a47b8d53c111;hp=c436fdaf526d52f258d82dfab37bbb0a571dc16e;hpb=45043cf804763d4cf93fec93d8294e385f87622a;p=u-boot

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index c436fdaf52..6d9347204b 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -11,7 +11,6 @@
 /* Virtual target or real hardware */
 #undef CONFIG_SOCFPGA_VIRTUAL_TARGET
 
-#define CONFIG_ARMV7
 #define CONFIG_SYS_THUMB_BUILD
 
 #define CONFIG_SOCFPGA
@@ -20,8 +19,7 @@
  * High level configuration
  */
 #define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO
-#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_DISPLAY_BOARDINFO_LATE
 #define CONFIG_ARCH_EARLY_INIT_R
 #define CONFIG_SYS_NO_FLASH
 #define CONFIG_CLOCKS
@@ -140,7 +138,7 @@
 #define CONFIG_DESIGNWARE_WATCHDOG
 #define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
 #define CONFIG_DW_WDT_CLOCK_KHZ		25000
-#define CONFIG_HW_WATCHDOG_TIMEOUT_MS	12000
+#define CONFIG_HW_WATCHDOG_TIMEOUT_MS	30000
 #endif
 
 /*
@@ -160,7 +158,7 @@
 #define CONFIG_SYS_MMC_MAX_BLK_COUNT	256	/* FIXME -- SPL only? */
 #endif
 
- /*
+/*
  * I2C support
  */
 #define CONFIG_SYS_I2C
@@ -187,6 +185,30 @@ unsigned int cm_get_l4_sp_clk_hz(void);
 #endif
 #define CONFIG_CMD_I2C
 
+/*
+ * QSPI support
+ */
+#ifdef CONFIG_OF_CONTROL	/* QSPI is controlled via DT */
+#define CONFIG_CADENCE_QSPI
+/* Enable multiple SPI NOR flash manufacturers */
+#define CONFIG_SPI_FLASH		/* SPI flash subsystem */
+#define CONFIG_SPI_FLASH_STMICRO	/* Micron/Numonyx flash */
+#define CONFIG_SPI_FLASH_SPANSION	/* Spansion flash */
+#define CONFIG_SPI_FLASH_MTD
+/* QSPI reference clock */
+#ifndef __ASSEMBLY__
+unsigned int cm_get_qspi_controller_clk_hz(void);
+#define CONFIG_CQSPI_REF_CLK		cm_get_qspi_controller_clk_hz()
+#endif
+#define CONFIG_CQSPI_DECODER		0
+#define CONFIG_CMD_SF
+#endif
+
+#ifdef CONFIG_OF_CONTROL	/* DW SPI is controlled via DT */
+#define CONFIG_DESIGNWARE_SPI
+#define CONFIG_CMD_SPI
+#endif
+
 /*
  * Serial Driver
  */