X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fspear3xx.h;h=37bdebb392c2072aa5b46febb52ba84713c52524;hb=4e8b7544b796c4a8d4513b4070716ce42bfba840;hp=012a84047f64d72d14216f0edccecc282de1c0ba;hpb=95da7841960723734518380aec64a062ebc4fb0d;p=u-boot

diff --git a/include/configs/spear3xx.h b/include/configs/spear3xx.h
old mode 100755
new mode 100644
index 012a84047f..37bdebb392
--- a/include/configs/spear3xx.h
+++ b/include/configs/spear3xx.h
@@ -28,15 +28,104 @@
  * High Level Configuration Options
  * (easy to change)
  */
+#if defined(CONFIG_spear300)
+#define CONFIG_SPEAR3XX				1
 #define CONFIG_SPEAR300				1
+#elif defined(CONFIG_spear310)
+#define CONFIG_SPEAR3XX				1
+#define CONFIG_SPEAR310				1
+#elif defined(CONFIG_spear320)
 #define CONFIG_SPEAR3XX				1
+#define CONFIG_SPEAR320				1
+#endif
 
 #include <configs/spear-common.h>
 
 /* Serial Configuration (PL011) */
 #define CONFIG_SYS_SERIAL0			0xD0000000
+
+#if defined(CONFIG_SPEAR300)
 #define CONFIG_PL01x_PORTS			{(void *)CONFIG_SYS_SERIAL0}
 
+#elif defined(CONFIG_SPEAR310)
+
+#if (CONFIG_CONS_INDEX)
+#undef  CONFIG_PL011_CLOCK
+#define CONFIG_PL011_CLOCK			(83 * 1000 * 1000)
+#endif
+
+#define CONFIG_SYS_SERIAL1			0xB2000000
+#define CONFIG_SYS_SERIAL2			0xB2080000
+#define CONFIG_SYS_SERIAL3			0xB2100000
+#define CONFIG_SYS_SERIAL4			0xB2180000
+#define CONFIG_SYS_SERIAL5			0xB2200000
+#define CONFIG_PL01x_PORTS			{(void *)CONFIG_SYS_SERIAL0, \
+						(void *)CONFIG_SYS_SERIAL1, \
+						(void *)CONFIG_SYS_SERIAL2, \
+						(void *)CONFIG_SYS_SERIAL3, \
+						(void *)CONFIG_SYS_SERIAL4, \
+						(void *)CONFIG_SYS_SERIAL5 }
+#elif defined(CONFIG_SPEAR320)
+
+#if (CONFIG_CONS_INDEX)
+#undef  CONFIG_PL011_CLOCK
+#define CONFIG_PL011_CLOCK			(83 * 1000 * 1000)
+#endif
+
+#define CONFIG_SYS_SERIAL1			0xA3000000
+#define CONFIG_SYS_SERIAL2			0xA4000000
+#define CONFIG_PL01x_PORTS			{(void *)CONFIG_SYS_SERIAL0, \
+						(void *)CONFIG_SYS_SERIAL1, \
+						(void *)CONFIG_SYS_SERIAL2 }
+#endif
+
+#if defined(CONFIG_SPEAR_EMI)
+
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+
+#if defined(CONFIG_SPEAR310)
+#define CONFIG_SYS_FLASH_BASE			0x50000000
+#define CONFIG_SYS_CS1_FLASH_BASE		0x60000000
+#define CONFIG_SYS_CS2_FLASH_BASE		0x70000000
+#define CONFIG_SYS_CS3_FLASH_BASE		0x80000000
+#define CONFIG_SYS_CS4_FLASH_BASE		0x90000000
+#define CONFIG_SYS_CS5_FLASH_BASE		0xA0000000
+#define CONFIG_SYS_FLASH_BANKS_LIST		{ CONFIG_SYS_FLASH_BASE,   \
+						CONFIG_SYS_CS1_FLASH_BASE, \
+						CONFIG_SYS_CS2_FLASH_BASE, \
+						CONFIG_SYS_CS3_FLASH_BASE, \
+						CONFIG_SYS_CS4_FLASH_BASE, \
+						CONFIG_SYS_CS5_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_BANKS		6
+
+#elif defined(CONFIG_SPEAR320)
+#define CONFIG_SYS_FLASH_BASE			0x44000000
+#define CONFIG_SYS_CS1_FLASH_BASE		0x45000000
+#define CONFIG_SYS_CS2_FLASH_BASE		0x46000000
+#define CONFIG_SYS_CS3_FLASH_BASE		0x47000000
+#define CONFIG_SYS_FLASH_BANKS_LIST		{ CONFIG_SYS_FLASH_BASE,   \
+						CONFIG_SYS_CS1_FLASH_BASE, \
+						CONFIG_SYS_CS2_FLASH_BASE, \
+						CONFIG_SYS_CS3_FLASH_BASE }
+#define CONFIG_SYS_MAX_FLASH_BANKS		4
+
+#endif
+
+#define CONFIG_SYS_MAX_FLASH_SECT		(127 + 8)
+#define CONFIG_SYS_FLASH_QUIET_TEST		1
+
+#endif
+
+#if defined(CONFIG_SPEAR300)
 #define CONFIG_SYS_NAND_BASE			(0x80000000)
 
+#elif defined(CONFIG_SPEAR310)
+#define CONFIG_SYS_NAND_BASE			(0x40000000)
+
+#elif defined(CONFIG_SPEAR320)
+#define CONFIG_SYS_NAND_BASE			(0x50000000)
+
+#endif
+
 #endif  /* __CONFIG_H */