X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Ftaurus.h;h=2cf4558daaffb22232b417b1aeea841715feb951;hb=84c7204bd18a0051a353c7a6f65a5666e1af9501;hp=ba9496fe5f0c7278b17f03685d3da430b6c55c82;hpb=50921cdc4474dafdcf19db54d7a669781ee5b70f;p=u-boot

diff --git a/include/configs/taurus.h b/include/configs/taurus.h
index ba9496fe5f..2cf4558daa 100644
--- a/include/configs/taurus.h
+++ b/include/configs/taurus.h
@@ -21,11 +21,13 @@
  */
 #include <asm/hardware.h>
 
-#define MACH_TYPE_TAURUS		2067
-#define MACH_TYPE_AXM			2068
-
 #define CONFIG_SYS_GENERIC_BOARD
 
+#if defined(CONFIG_SPL_BUILD)
+#define CONFIG_SYS_THUMB_BUILD
+#define CONFIG_SYS_ICACHE_OFF
+#define CONFIG_SYS_DCACHE_OFF
+#endif
 /*
  * Warning: changing CONFIG_SYS_TEXT_BASE requires
  * adapting the initial boot program.
@@ -34,7 +36,7 @@
  */
 
 
-#define CONFIG_SYS_TEXT_BASE		0x23f00000
+#define CONFIG_SYS_TEXT_BASE		0x21000000
 
 /* ARM asynchronous clock */
 #define CONFIG_SYS_AT91_SLOW_CLOCK	32768		/* slow clock xtal */
@@ -116,6 +118,12 @@
 #define CONFIG_RMII
 #define CONFIG_AT91_WANTS_COMMON_PHY
 
+#define CONFIG_AT91SAM9_WATCHDOG
+#if !defined(CONFIG_SPL_BUILD)
+/* Enable the watchdog */
+#define CONFIG_HW_WATCHDOG
+#endif
+
 /* USB */
 #if defined(CONFIG_BOARD_TAURUS)
 #define CONFIG_USB_ATMEL
@@ -137,6 +145,19 @@
 #define TAURUS_SPI_MASK (1 << 4)
 #define TAURUS_SPI_CS_PIN	AT91_PIN_PA3
 
+#if defined(CONFIG_SPL_BUILD)
+/* SPL related */
+#undef CONFIG_SPL_OS_BOOT		/* Not supported by existing map */
+#define CONFIG_SPL_SPI_SUPPORT
+#define CONFIG_SPL_SPI_FLASH_SUPPORT
+#define CONFIG_SPL_SPI_LOAD
+#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x20000
+
+#define CONFIG_SF_DEFAULT_BUS 0
+#define CONFIG_SF_DEFAULT_SPEED 10000000
+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
+#endif
+
 /* load address */
 #define CONFIG_SYS_LOAD_ADDR			0x22000000
 
@@ -168,4 +189,57 @@
 #define CONFIG_SYS_MALLOC_LEN \
 	ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
 
+/* Defines for SPL */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_TEXT_BASE		0x0
+#define CONFIG_SPL_MAX_SIZE		(14 * 1024)
+#define CONFIG_SPL_STACK		(16 * 1024)
+#define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE - \
+					CONFIG_SYS_MALLOC_LEN)
+#define CONFIG_SYS_SPL_MALLOC_SIZE      CONFIG_SYS_MALLOC_LEN
+
+#define CONFIG_SPL_BSS_START_ADDR	CONFIG_SPL_MAX_SIZE
+#define CONFIG_SPL_BSS_MAX_SIZE		(3 * 1024)
+
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+
+#define CONFIG_SPL_BOARD_INIT
+#define CONFIG_SPL_GPIO_SUPPORT
+#define CONFIG_SYS_NAND_ENABLE_PIN_SPL	(2*32 + 14)
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SYS_USE_NANDFLASH	1
+#define CONFIG_SPL_NAND_DRIVERS
+#define CONFIG_SPL_NAND_BASE
+#define CONFIG_SPL_NAND_ECC
+#define CONFIG_SPL_NAND_RAW_ONLY
+#define CONFIG_SPL_NAND_SOFTECC
+#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x20000
+#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
+#define	CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_U_BOOT_DST	CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_NAND_5_ADDR_CYCLE
+
+#define CONFIG_SYS_NAND_SIZE		(256*1024*1024)
+#define CONFIG_SYS_NAND_PAGE_SIZE	2048
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
+#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
+					 CONFIG_SYS_NAND_PAGE_SIZE)
+#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
+#define CONFIG_SYS_NAND_ECCSIZE		256
+#define CONFIG_SYS_NAND_ECCBYTES	3
+#define CONFIG_SYS_NAND_OOBSIZE		64
+#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
+					  48, 49, 50, 51, 52, 53, 54, 55, \
+					  56, 57, 58, 59, 60, 61, 62, 63, }
+
+
+#define CONFIG_SPL_ATMEL_SIZE
+#define CONFIG_SYS_MASTER_CLOCK		132096000
+#define AT91_PLL_LOCK_TIMEOUT		1000000
+#define CONFIG_SYS_AT91_PLLA		0x202A3F01
+#define CONFIG_SYS_MCKR			0x1300
+#define CONFIG_SYS_MCKR_CSS		(0x02 | CONFIG_SYS_MCKR)
+#define CONFIG_SYS_AT91_PLLB		0x10193F05
 #endif