X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fti_omap3_common.h;h=32877d1964ded5db4c4d5af15bb9ccd36573cced;hb=63865278dae47ad19527d9f9b6e0dad6cb01f401;hp=854cb78882d1b580e64594b78f0f6194eefce9f1;hpb=e97f9d817e600cd6f43d1d0da76f5787e33a5c56;p=u-boot

diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h
index 854cb78882..32877d1964 100644
--- a/include/configs/ti_omap3_common.h
+++ b/include/configs/ti_omap3_common.h
@@ -14,10 +14,19 @@
 #ifndef __CONFIG_TI_OMAP3_COMMON_H__
 #define __CONFIG_TI_OMAP3_COMMON_H__
 
-#define CONFIG_OMAP34XX
+/*
+ * High Level Configuration Options
+ */
+
+#define CONFIG_SYS_CACHELINE_SIZE	64
 
 #include <asm/arch/cpu.h>
-#include <asm/arch/omap3.h>
+#include <asm/arch/omap.h>
+
+/* Common ARM Erratas */
+#define CONFIG_ARM_ERRATA_454179
+#define CONFIG_ARM_ERRATA_430973
+#define CONFIG_ARM_ERRATA_621766
 
 /* The chip has SDRC controller */
 #define CONFIG_SDRC
@@ -28,17 +37,20 @@
 
 /* NS16550 Configuration */
 #define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
 #define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK
+#ifdef CONFIG_SPL_BUILD
+# define CONFIG_SYS_NS16550_SERIAL
+# define CONFIG_SYS_NS16550_REG_SIZE	(-4)
+#endif
 #define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600, \
 					115200}
 
 /* Select serial console configuration */
 #define CONFIG_CONS_INDEX		3
+#ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
 #define CONFIG_SERIAL3			3
+#endif
 
 /* Physical Memory Map */
 #define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
@@ -54,20 +66,22 @@
 #define CONFIG_SYS_MONITOR_LEN		(256 << 10)
 
 /* TWL4030 */
-#define CONFIG_TWL4030_POWER		1
+#define CONFIG_TWL4030_POWER
 
 /* SPL */
 #define CONFIG_SPL_TEXT_BASE		0x40200800
 #define CONFIG_SPL_MAX_SIZE		(54 * 1024)
 #define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"
 #define CONFIG_SPL_POWER_SUPPORT
+#define CONFIG_SYS_SPL_ARGS_ADDR	(CONFIG_SYS_SDRAM_BASE + \
+					 (64 << 20))
 
 #ifdef CONFIG_NAND
-#define CONFIG_SPL_NAND_SUPPORT
 #define CONFIG_SPL_NAND_SIMPLE
+#define CONFIG_SYS_NAND_BASE		0x30000000
 #endif
 
 /* Now bring in the rest of the common code. */
-#include <configs/ti_armv7_common.h>
+#include <configs/ti_armv7_omap.h>
 
 #endif	/* __CONFIG_TI_OMAP3_COMMON_H__ */