X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Ftrizepsiv.h;h=2d55044ededb15eb915422fbaefe6e3fe83833a6;hb=4e8b7544b796c4a8d4513b4070716ce42bfba840;hp=ac3566cad16475fd3378d707d79d31c5d285af44;hpb=cc72ac660de1979fced752bf740afb54cb3bed0a;p=u-boot

diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h
index ac3566cad1..2d55044ede 100644
--- a/include/configs/trizepsiv.h
+++ b/include/configs/trizepsiv.h
@@ -43,13 +43,13 @@
 #define CONFIG_PXA27X		1	/* This is an PXA27x CPU    */
 
 #define CONFIG_MMC		1
-#define BOARD_LATE_INIT		1
+#define CONFIG_BOARD_LATE_INIT
 #define	CONFIG_SYS_TEXT_BASE	0x0
 
 #undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
 
 /* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
+#define CONFIG_SYS_DCACHE_OFF
 
 #define RTC
 
@@ -57,7 +57,6 @@
  * Size of malloc() pool
  */
 #define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Hardware drivers
@@ -214,7 +213,7 @@
 #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
 
 /*
  * GPIO settings
@@ -292,7 +291,6 @@
 #define CONFIG_SYS_MCIO0_VAL		0x00008407
 #define CONFIG_SYS_MCIO1_VAL		0x0000c108
 
-#define CONFIG_NET_MULTI		1
 #define CONFIG_DRIVER_DM9000		1
 
 #if CONFIG_POLARIS