X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fxaeniax.h;h=2999d1b0f54ddd55e7473c83878c6644aec296f6;hb=1018b0a56a4719a64fb6867337a72d6a9343008b;hp=1329f0f3d85a1748162c4a3f0cd5e33e452ea50f;hpb=0bf7de838096e804f0cece8f2d94905477381b6e;p=u-boot

diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h
index 1329f0f3d8..2999d1b0f5 100644
--- a/include/configs/xaeniax.h
+++ b/include/configs/xaeniax.h
@@ -14,23 +14,7 @@
  *
  * Configuation settings for the xaeniax board.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef __CONFIG_H
@@ -40,24 +24,21 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_PXA250		1	/* This is an PXA255 CPU    */
+#define CONFIG_CPU_PXA25X		1	/* This is an PXA255 CPU    */
 #define CONFIG_XAENIAX		1	/* on a xaeniax board	    */
+#define	CONFIG_SYS_TEXT_BASE	0x0
 
-
-#define BOARD_LATE_INIT		1
-
-
-#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff */
+#define CONFIG_BOARD_LATE_INIT
 
 /* we will never enable dcache, because we have to setup MMU first */
-#define CONFIG_SYS_NO_DCACHE
+#define CONFIG_SYS_DCACHE_OFF
 
 /*
  * select serial console configuration
  */
 #define CONFIG_PXA_SERIAL
 #define CONFIG_BTUART	       1       /* we use BTUART on XAENIAX */
-
+#define CONFIG_CONS_INDEX	4
 
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
@@ -66,9 +47,6 @@
 
 #define CONFIG_BAUDRATE		115200
 
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 } /* valid baudrates */
-
-
 /*
  * BOOTP options
  */
@@ -106,7 +84,6 @@
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	115200			/* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX	1			/* which serial port to use */
 #endif
 
 /*
@@ -114,7 +91,6 @@
  * used for the RAM copy of the uboot code
  */
 #define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Miscellaneous configurable options
@@ -122,7 +98,6 @@
 #define CONFIG_SYS_LONGHELP				/* undef to save memory	*/
 #define CONFIG_SYS_HUSH_PARSER		1
 
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
 
 #ifdef CONFIG_SYS_HUSH_PARSER
 #define CONFIG_SYS_PROMPT		"u-boot$ "	/* Monitor Command Prompt */
@@ -140,7 +115,6 @@
 
 #define CONFIG_SYS_LOAD_ADDR		0xa1000000	/* default load address */
 
-#define CONFIG_SYS_HZ			1000
 #define CONFIG_SYS_CPUSPEED		0x141		/* set core clock to 400/200/100 MHz */
 
 /*
@@ -167,6 +141,9 @@
 
 #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
+#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
+#define	CONFIG_SYS_INIT_SP_ADDR		0xfffff800
+
 /*
  * FLASH and environment organization
  */
@@ -182,21 +159,9 @@
 #define CONFIG_ENV_ADDR		(PHYS_FLASH_1 + 0x40000)/* Addr of Environment Sector	*/
 #define CONFIG_ENV_SIZE		0x40000			/* Total Size of Environment Sector	*/
 
-/*
- * Stack sizes
- *
- * The stack sizes are set up in start.S using the settings below
- */
-#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */
-#ifdef CONFIG_USE_IRQ
-#define CONFIG_STACKSIZE_IRQ	(4*1024)	/* IRQ stack */
-#define CONFIG_STACKSIZE_FIQ	(4*1024)	/* FIQ stack */
-#endif
-
 /*
  * SMSC91C111 Network Card
  */
-#define CONFIG_NET_MULTI
 #define CONFIG_SMC91111		1
 #define CONFIG_SMC91111_BASE		0x10000300  /* chip select 3         */
 #define CONFIG_SMC_USE_32_BIT		1          /* 32 bit bus  */
@@ -434,8 +399,9 @@
  */
 #define CONFIG_SYS_PSSR_VAL		0x00000030
 
-#define CONFIG_SYS_CKEN_VAL            0x00000080  /*  */
-#define CONFIG_SYS_ICMR_VAL            0x00000000  /* No interrupts enabled        */
+#define CONFIG_SYS_CKEN			0x00000080  /*  */
+#define CONFIG_SYS_ICMR			0x00000000  /* No interrupts enabled        */
+#define	CONFIG_SYS_CCCR			CCCR_L27|CCCR_M2|CCCR_N10
 
 
 /*
@@ -559,6 +525,9 @@
  */
 #define CONFIG_SYS_MDMRS_VAL		0x00320032
 
+#define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
+#define	CONFIG_SYS_SXCNFG_VAL		0x00000000
+
 /*
  * PCMCIA and CF Interfaces
  */