X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fxaeniax.h;h=a75c426dfa21e32324bccafebb253a2bf5fae723;hb=2a9a2339a4ea04636ed0968e76eeaf784e987f52;hp=67d4106d6f1b8a5d0b96e95f1c40dcf5b591f3c1;hpb=6ef6eb91cda895de3366068fc2caf25328786f4d;p=u-boot

diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h
index 67d4106d6f..a75c426dfa 100644
--- a/include/configs/xaeniax.h
+++ b/include/configs/xaeniax.h
@@ -42,6 +42,7 @@
  */
 #define CONFIG_PXA250		1	/* This is an PXA255 CPU    */
 #define CONFIG_XAENIAX		1	/* on a xaeniax board	    */
+#define	CONFIG_SYS_TEXT_BASE	0x0
 
 
 #define BOARD_LATE_INIT		1
@@ -114,7 +115,6 @@
  * used for the RAM copy of the uboot code
  */
 #define CONFIG_SYS_MALLOC_LEN	    (CONFIG_ENV_SIZE + 128*1024)
-#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
 
 /*
  * Miscellaneous configurable options
@@ -168,7 +168,7 @@
 #define CONFIG_SYS_FLASH_BASE		PHYS_FLASH_1
 
 #define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
-#define	CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_GBL_DATA_SIZE + PHYS_SDRAM_1)
+#define	CONFIG_SYS_INIT_SP_ADDR		(GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
 
 /*
  * FLASH and environment organization
@@ -437,8 +437,9 @@
  */
 #define CONFIG_SYS_PSSR_VAL		0x00000030
 
-#define CONFIG_SYS_CKEN_VAL            0x00000080  /*  */
-#define CONFIG_SYS_ICMR_VAL            0x00000000  /* No interrupts enabled        */
+#define CONFIG_SYS_CKEN			0x00000080  /*  */
+#define CONFIG_SYS_ICMR			0x00000000  /* No interrupts enabled        */
+#define	CONFIG_SYS_CCCR			CCCR_L27|CCCR_M2|CCCR_N10
 
 
 /*
@@ -562,6 +563,9 @@
  */
 #define CONFIG_SYS_MDMRS_VAL		0x00320032
 
+#define	CONFIG_SYS_FLYCNFG_VAL		0x00000000
+#define	CONFIG_SYS_SXCNFG_VAL		0x00000000
+
 /*
  * PCMCIA and CF Interfaces
  */