X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fxpedite537x.h;h=6a469bb6026c31bf0e698338a2504018052fd611;hb=f3fcf92d595b297b47a1b58b8ec39f93f40ef912;hp=e7de13a7ccb58ec9f545a9d965d37d0f0953e2fb;hpb=f2b382ea066d02d5ba44870024cc1295e85782ef;p=u-boot diff --git a/include/configs/xpedite537x.h b/include/configs/xpedite537x.h index e7de13a7cc..6a469bb602 100644 --- a/include/configs/xpedite537x.h +++ b/include/configs/xpedite537x.h @@ -96,14 +96,8 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); #define CONFIG_BTB /* toggle branch predition */ #define CONFIG_ENABLE_36BIT_PHYS 1 -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xef000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_CCSRBAR 0xef000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* * Diagnostics @@ -224,10 +218,9 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); */ #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000 -#define CONFIG_SYS_INIT_RAM_END 0x00004000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ @@ -253,7 +246,6 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); * Use the HUSH parser */ #define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /* * Pass open firmware flat tree @@ -370,12 +362,21 @@ extern unsigned long get_board_ddr_clk(unsigned long dummy); */ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ -#define CONFIG_NET_MULTI 1 #define CONFIG_TSEC_TBI #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ #define CONFIG_ETHPRIME "eTSEC2" +/* + * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force + * 1000mbps SGMII link + */ +#define CONFIG_TSEC_TBICR_SETTINGS ( \ + TBICR_PHY_RESET \ + | TBICR_FULL_DUPLEX \ + | TBICR_SPEED1_SET \ + ) + #define CONFIG_TSEC1 1 #define CONFIG_TSEC1_NAME "eTSEC1" #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)