X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fyucca.h;h=0b4dfb8e73f1df0bc839dd8e2ca8893f48524aa6;hb=c57cca255ce403fdfe77e7b040b578a29514da0b;hp=b165bd7a118d330a004b61eb01a25cbe52f4e9f4;hpb=50bd0057ba8fceeb48533f8b1a652ccd0e170838;p=u-boot

diff --git a/include/configs/yucca.h b/include/configs/yucca.h
index b165bd7a11..0b4dfb8e73 100644
--- a/include/configs/yucca.h
+++ b/include/configs/yucca.h
@@ -37,6 +37,7 @@
 #define CONFIG_4xx			1	/* ... PPC4xx family	*/
 #define CONFIG_440			1	/* ... PPC440 family	*/
 #define CONFIG_440SPE			1	/* Specifc SPe support	*/
+#define CONFIG_440SPE_REVA		1	/* Support old Rev A.	*/
 #define CONFIG_BOARD_EARLY_INIT_F	1	/* Call board_pre_init	*/
 #define CONFIG_SYS_CLK_FREQ	33333333	/* external freq to pll	*/
 #define EXTCLK_33_33		33333333
@@ -389,6 +390,11 @@
 #define FPGA_REG1A_PE_SELSOURCE_0	0x0002
 #define FPGA_REG1A_PE_SELSOURCE_1	0x0001
 
+#define FPGA_REG1A_GLED_ENCODE(n)	(FPGA_REG1A_PE0_GLED >> (n))
+#define FPGA_REG1A_YLED_ENCODE(n)	(FPGA_REG1A_PE0_YLED >> (n))
+#define FPGA_REG1A_PWRON_ENCODE(n)	(FPGA_REG1A_PE0_PWRON >> (n))
+#define FPGA_REG1A_REFCLK_ENCODE(n)	(FPGA_REG1A_PE0_REFCLK_ENABLE >> (n))
+
 /*----------------------------------------------------------------------------+
 | PCIe Miscellaneous
 +----------------------------------------------------------------------------*/
@@ -407,6 +413,9 @@
 #define FPGA_REG1C_PE1_PERST		0x0008
 #define FPGA_REG1C_PE2_PERST		0x0004
 
+#define FPGA_REG1C_ROOTPOINT_ENCODE(n)	(FPGA_REG1C_PE0_ROOTPOINT >> (n))
+#define FPGA_REG1C_PERST_ENCODE(n)	(FPGA_REG1C_PE0_PERST >> (n))
+
 /*----------------------------------------------------------------------------+
 | Defines
 +----------------------------------------------------------------------------*/