X-Git-Url: https://git.sur5r.net/?a=blobdiff_plain;f=include%2Fconfigs%2Fyucca.h;h=6f9d3e3c6f3477f56c06a4ef6dbc0b17b8eb616e;hb=a00eccfebc954ad9485161efeca7d9aaf626d530;hp=74033b4aef43af04f910ca0eae339e397b275063;hpb=d4d1e9bee7c45ea8c513d3af697c864107f1c4d1;p=u-boot diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 74033b4aef..6f9d3e3c6f 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -64,7 +64,7 @@ #define CFG_PCI_TARGBASE CFG_PCI_MEMBASE #define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */ -#define CFG_PCIE_MEMSIZE 0x01000000 +#define CFG_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */ #define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */ #define CFG_PCIE0_CFGBASE 0xc0000000 @@ -74,6 +74,9 @@ #define CFG_PCIE1_XCFGBASE 0xc3001000 #define CFG_PCIE2_XCFGBASE 0xc3002000 +/* base address of inbound PCIe window */ +#define CFG_PCIE_INBOUND_BASE 0x0000000400000000ULL + /* System RAM mapped to PCI space */ #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE @@ -151,7 +154,7 @@ #define CONFIG_ENV_OVERWRITE 1 #define CONFIG_PREBOOT "echo;" \ - "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ "echo" #undef CONFIG_BOOTARGS @@ -172,7 +175,7 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ "bootfile=yucca/uImage\0" \ "kernel_addr=E7F10000\0" \ "ramdisk_addr=E7F20000\0" \ @@ -181,8 +184,9 @@ "update=protect off 2:4-7;era 2:4-7;" \ "cp.b ${fileaddr} FFFB0000 ${filesize};" \ "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ + "upd=run load update\0" \ "pciconfighost=1\0" \ + "pcie_mode=RP:EP:EP\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" @@ -320,14 +324,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/ -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if defined(CONFIG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif /* * Internal Definitions @@ -545,4 +541,8 @@ /*---------------------------------------------------------------------------*/ +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */